From: Segher Boessenkool Date: Mon, 22 Jun 2020 20:15:46 +0000 (+0000) Subject: rs6000: Rename future to power10 X-Git-Tag: releases/gcc-10.2.0~113 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9913aa6fbc42eab81fc9599a7d4636de2f92c00b;p=thirdparty%2Fgcc.git rs6000: Rename future to power10 == The actual changelog had == Backport from trunk == 2020-06-22 Segher Boessenkool == but the commit scripts refuse that 2020-06-30 Segher Boessenkool * config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10 on AIX, and -mpower10 elsewhere. * config/rs6000/future.md: Delete. * config/rs6000/linux64.h: Update comments. Use TARGET_POWER10, not TARGET_FUTURE. * config/rs6000/power10.md: New file. * config/rs6000/rs6000-builtin.def: Update comments. * config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*. Update compiler messages. * config/rs6000/rs6000-cpus.def: Update comments. Use ISA_3_1_*, not ISA_FUTURE_*. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. * config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. * config/rs6000/rs6000-string.c: Ditto. * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10" instead of "future", reorder it to right after "power9". * config/rs6000/rs6000.c: Update comments. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use TARGET_POWER10, not TARGET_FUTURE. Use RS6000_BTM_P10, not RS6000_BTM_FUTURE. Update compiler messages. Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. Use ISA_3_1_MASKS_SERVER, not ISA_FUTURE_MASKS_SERVER. (rs6000_opt_masks): Use "power10" instead of "future". (rs6000_builtin_mask_names): Ditto. (rs6000_disable_incompatible_switches): Ditto. * config/rs6000/rs6000.h: Use -mpower10, not -mfuture. Use -mcpu=power10, not -mcpu=future. Use MASK_POWER10, not MASK_FUTURE. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use RS6000_BTM_P10, not RS6000_BTM_FUTURE. * config/rs6000/rs6000.md: Use "power10", not "future". Use TARGET_POWER10, not TARGET_FUTURE. Include "power10.md", not "future.md". * config/rs6000/rs6000.opt (mfuture): Delete. (mpower10): New. * config/rs6000/t-rs6000: Use "power10.md", not "future.md". * config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE. --- diff --git a/gcc/config/rs6000/driver-rs6000.c b/gcc/config/rs6000/driver-rs6000.c index 169506ab86b0..6b6439cb9c28 100644 --- a/gcc/config/rs6000/driver-rs6000.c +++ b/gcc/config/rs6000/driver-rs6000.c @@ -447,6 +447,7 @@ static const struct asm_name asm_names[] = { { "power7", "-mpwr7" }, { "power8", "-mpwr8" }, { "power9", "-mpwr9" }, + { "power10", "-mpwr10" }, { "powerpc", "-mppc" }, { "rs64", "-mppc" }, { "603", "-m603" }, @@ -457,7 +458,6 @@ static const struct asm_name asm_names[] = { { "630", "-m620" }, { "970", "-m970" }, { "G5", "-m970" }, - { "future", "-mfuture" }, { NULL, "\ %{mvsx: -mpwr6; \ maltivec: -m970; \ @@ -475,6 +475,7 @@ static const struct asm_name asm_names[] = { { "power7", "-mpower7" }, { "power8", "%{mpower9-vector:-mpower9;:-mpower8}" }, { "power9", "-mpower9" }, + { "power10", "-mpower10" }, { "a2", "-ma2" }, { "powerpc", "-mppc" }, { "powerpc64", "-mppc64" }, @@ -521,7 +522,6 @@ static const struct asm_name asm_names[] = { { "e5500", "-me5500" }, { "e6500", "-me6500" }, { "titan", "-mtitan" }, - { "future", "-mfuture" }, { NULL, "\ %{mpower9-vector: -mpower9; \ mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ diff --git a/gcc/config/rs6000/future.md b/gcc/config/rs6000/future.md deleted file mode 100644 index 3200f3acf054..000000000000 --- a/gcc/config/rs6000/future.md +++ /dev/null @@ -1,521 +0,0 @@ -;; Scheduling description for a future IBM processor. -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. -;; -;; This is a clone of power9.md. It is intended to be a placeholder until a -;; real scheduler module can be contributed. -;; The original power9.md was contributed by Pat Haugen (pthaugen@us.ibm.com). - -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. -;; -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. -;; -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; . -;; -;; This file was cloned from power9.md. In the future, we will have future -;; specific optimizations here. - -(define_automaton "futuredsp,futurelsu,futurevsu,futurefpdiv,futuremisc") - -(define_cpu_unit "lsu0_future,lsu1_future,lsu2_future,lsu3_future" "futurelsu") -(define_cpu_unit "vsu0_future,vsu1_future,vsu2_future,vsu3_future" "futurevsu") -; Two vector permute units, part of vsu -(define_cpu_unit "prm0_future,prm1_future" "futurevsu") -; Two fixed point divide units, not pipelined -(define_cpu_unit "fx_div0_future,fx_div1_future" "futuremisc") -(define_cpu_unit "bru_future,cryptu_future,dfu_future" "futuremisc") -; Create a false unit for use by non-pipelined FP div/sqrt -(define_cpu_unit "fp_div0_future,fp_div1_future,fp_div2_future,fp_div3_future" - "futurefpdiv") - - -(define_cpu_unit "x0_future,x1_future,xa0_future,xa1_future, - x2_future,x3_future,xb0_future,xb1_future, - br0_future,br1_future" "futuredsp") - - -; Dispatch port reservations -; -; Future can dispatch a maximum of 6 iops per cycle with the following -; general restrictions (other restrictions also apply): -; 1) At most 2 iops per execution slice -; 2) At most 2 iops to the branch unit -; Note that insn position in a dispatch group of 6 insns does not infer which -; execution slice the insn is routed to. The units are used to infer the -; conflicts that exist (i.e. an 'even' requirement will preclude dispatch -; with 2 insns with 'superslice' requirement). - -; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but -; are listed as separate units to allow those insns that preclude its use to -; still be scheduled two to a superslice while reserving the 3rd slot. The -; same applies for xb0/xb1. -(define_reservation "DU_xa_future" "xa0_future+xa1_future") -(define_reservation "DU_xb_future" "xb0_future+xb1_future") - -; Any execution slice dispatch -(define_reservation "DU_any_future" - "x0_future|x1_future|DU_xa_future|x2_future|x3_future| - DU_xb_future") - -; Even slice, actually takes even/odd slots -(define_reservation "DU_even_future" "x0_future+x1_future|x2_future+x3_future") - -; Slice plus 3rd slot -(define_reservation "DU_slice_3_future" - "x0_future+xa0_future|x1_future+xa1_future| - x2_future+xb0_future|x3_future+xb1_future") - -; Superslice -(define_reservation "DU_super_future" - "x0_future+x1_future|x2_future+x3_future") - -; 2-way cracked -(define_reservation "DU_C2_future" "x0_future+x1_future| - x1_future+DU_xa_future| - x1_future+x2_future| - DU_xa_future+x2_future| - x2_future+x3_future| - x3_future+DU_xb_future") - -; 2-way cracked plus 3rd slot -(define_reservation "DU_C2_3_future" "x0_future+x1_future+xa0_future| - x1_future+x2_future+xa1_future| - x2_future+x3_future+xb0_future") - -; 3-way cracked (consumes whole decode/dispatch cycle) -(define_reservation "DU_C3_future" - "x0_future+x1_future+xa0_future+xa1_future+x2_future+ - x3_future+xb0_future+xb1_future+br0_future+br1_future") - -; Branch ports -(define_reservation "DU_branch_future" "br0_future|br1_future") - - -; Execution unit reservations -(define_reservation "LSU_future" - "lsu0_future|lsu1_future|lsu2_future|lsu3_future") - -(define_reservation "LSU_pair_future" - "lsu0_future+lsu1_future|lsu1_future+lsu2_future| - lsu2_future+lsu3_future|lsu3_future+lsu0_future") - -(define_reservation "VSU_future" - "vsu0_future|vsu1_future|vsu2_future|vsu3_future") - -(define_reservation "VSU_super_future" - "vsu0_future+vsu1_future|vsu2_future+vsu3_future") - -(define_reservation "VSU_PRM_future" "prm0_future|prm1_future") - -; Define the reservation to be used by FP div/sqrt which allows other insns -; to be issued to the VSU, but blocks other div/sqrt for a number of cycles. -; Note that the number of cycles blocked varies depending on insn, but we -; just use the same number for all in order to keep the number of DFA states -; reasonable. -(define_reservation "FP_DIV_future" - "fp_div0_future*8|fp_div1_future*8|fp_div2_future*8| - fp_div3_future*8") -(define_reservation "VEC_DIV_future" - "fp_div0_future*8+fp_div1_future*8| - fp_div2_future*8+fp_div3_future*8") - - -; LS Unit -(define_insn_reservation "future-load" 4 - (and (eq_attr "type" "load") - (eq_attr "sign_extend" "no") - (eq_attr "update" "no") - (eq_attr "cpu" "future")) - "DU_any_future,LSU_future") - -(define_insn_reservation "future-load-update" 4 - (and (eq_attr "type" "load") - (eq_attr "sign_extend" "no") - (eq_attr "update" "yes") - (eq_attr "cpu" "future")) - "DU_C2_future,LSU_future+VSU_future") - -(define_insn_reservation "future-load-ext" 6 - (and (eq_attr "type" "load") - (eq_attr "sign_extend" "yes") - (eq_attr "update" "no") - (eq_attr "cpu" "future")) - "DU_C2_future,LSU_future") - -(define_insn_reservation "future-load-ext-update" 6 - (and (eq_attr "type" "load") - (eq_attr "sign_extend" "yes") - (eq_attr "update" "yes") - (eq_attr "cpu" "future")) - "DU_C3_future,LSU_future+VSU_future") - -(define_insn_reservation "future-fpload-double" 4 - (and (eq_attr "type" "fpload") - (eq_attr "update" "no") - (eq_attr "size" "64") - (eq_attr "cpu" "future")) - "DU_slice_3_future,LSU_future") - -(define_insn_reservation "future-fpload-update-double" 4 - (and (eq_attr "type" "fpload") - (eq_attr "update" "yes") - (eq_attr "size" "64") - (eq_attr "cpu" "future")) - "DU_C2_3_future,LSU_future+VSU_future") - -; SFmode loads are cracked and have additional 2 cycles over DFmode -(define_insn_reservation "future-fpload-single" 6 - (and (eq_attr "type" "fpload") - (eq_attr "update" "no") - (eq_attr "size" "32") - (eq_attr "cpu" "future")) - "DU_C2_3_future,LSU_future") - -(define_insn_reservation "future-fpload-update-single" 6 - (and (eq_attr "type" "fpload") - (eq_attr "update" "yes") - (eq_attr "size" "32") - (eq_attr "cpu" "future")) - "DU_C3_future,LSU_future+VSU_future") - -(define_insn_reservation "future-vecload" 5 - (and (eq_attr "type" "vecload") - (eq_attr "cpu" "future")) - "DU_any_future,LSU_pair_future") - -; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store -(define_insn_reservation "future-store" 0 - (and (eq_attr "type" "store") - (eq_attr "update" "no") - (eq_attr "indexed" "no") - (eq_attr "cpu" "future")) - "DU_slice_3_future,LSU_future") - -(define_insn_reservation "future-store-indexed" 0 - (and (eq_attr "type" "store") - (eq_attr "update" "no") - (eq_attr "indexed" "yes") - (eq_attr "cpu" "future")) - "DU_slice_3_future,LSU_future") - -; Update forms have 2 cycle latency for updated addr reg -(define_insn_reservation "future-store-update" 2 - (and (eq_attr "type" "store") - (eq_attr "update" "yes") - (eq_attr "indexed" "no") - (eq_attr "cpu" "future")) - "DU_C2_3_future,LSU_future+VSU_future") - -; Update forms have 2 cycle latency for updated addr reg -(define_insn_reservation "future-store-update-indexed" 2 - (and (eq_attr "type" "store") - (eq_attr "update" "yes") - (eq_attr "indexed" "yes") - (eq_attr "cpu" "future")) - "DU_C2_3_future,LSU_future+VSU_future") - -(define_insn_reservation "future-fpstore" 0 - (and (eq_attr "type" "fpstore") - (eq_attr "update" "no") - (eq_attr "cpu" "future")) - "DU_slice_3_future,LSU_future") - -; Update forms have 2 cycle latency for updated addr reg -(define_insn_reservation "future-fpstore-update" 2 - (and (eq_attr "type" "fpstore") - (eq_attr "update" "yes") - (eq_attr "cpu" "future")) - "DU_C2_3_future,LSU_future+VSU_future") - -(define_insn_reservation "future-vecstore" 0 - (and (eq_attr "type" "vecstore") - (eq_attr "cpu" "future")) - "DU_super_future,LSU_pair_future") - -(define_insn_reservation "future-larx" 4 - (and (eq_attr "type" "load_l") - (eq_attr "cpu" "future")) - "DU_any_future,LSU_future") - -(define_insn_reservation "future-stcx" 2 - (and (eq_attr "type" "store_c") - (eq_attr "cpu" "future")) - "DU_C2_3_future,LSU_future+VSU_future") - -(define_insn_reservation "future-sync" 4 - (and (eq_attr "type" "sync,isync") - (eq_attr "cpu" "future")) - "DU_any_future,LSU_future") - - -; VSU Execution Unit - -; Fixed point ops - -; Most ALU insns are simple 2 cycle, including record form -(define_insn_reservation "future-alu" 2 - (and (eq_attr "type" "add,exts,integer,logical,isel") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") -; 5 cycle CR latency -(define_bypass 5 "future-alu" - "future-crlogical,future-mfcr,future-mfcrf") - -; Rotate/shift prevent use of third slot -(define_insn_reservation "future-rot" 2 - (and (eq_attr "type" "insert,shift") - (eq_attr "dot" "no") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future") - -; Record form rotate/shift are cracked -(define_insn_reservation "future-cracked-alu" 2 - (and (eq_attr "type" "insert,shift") - (eq_attr "dot" "yes") - (eq_attr "cpu" "future")) - "DU_C2_3_future,VSU_future") -; 7 cycle CR latency -(define_bypass 7 "future-cracked-alu" - "future-crlogical,future-mfcr,future-mfcrf") - -(define_insn_reservation "future-alu2" 3 - (and (eq_attr "type" "cntlz,popcnt,trap") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") -; 6 cycle CR latency -(define_bypass 6 "future-alu2" - "future-crlogical,future-mfcr,future-mfcrf") - -(define_insn_reservation "future-cmp" 2 - (and (eq_attr "type" "cmp") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") - - -; Treat 'two' and 'three' types as 2 or 3 way cracked -(define_insn_reservation "future-two" 4 - (and (eq_attr "type" "two") - (eq_attr "cpu" "future")) - "DU_C2_future,VSU_future") - -(define_insn_reservation "future-three" 6 - (and (eq_attr "type" "three") - (eq_attr "cpu" "future")) - "DU_C3_future,VSU_future") - -(define_insn_reservation "future-mul" 5 - (and (eq_attr "type" "mul") - (eq_attr "dot" "no") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future") - -(define_insn_reservation "future-mul-compare" 5 - (and (eq_attr "type" "mul") - (eq_attr "dot" "yes") - (eq_attr "cpu" "future")) - "DU_C2_3_future,VSU_future") -; 10 cycle CR latency -(define_bypass 10 "future-mul-compare" - "future-crlogical,future-mfcr,future-mfcrf") - -; Fixed point divides reserve the divide units for a minimum of 8 cycles -(define_insn_reservation "future-idiv" 16 - (and (eq_attr "type" "div") - (eq_attr "size" "32") - (eq_attr "cpu" "future")) - "DU_even_future,fx_div0_future*8|fx_div1_future*8") - -(define_insn_reservation "future-ldiv" 24 - (and (eq_attr "type" "div") - (eq_attr "size" "64") - (eq_attr "cpu" "future")) - "DU_even_future,fx_div0_future*8|fx_div1_future*8") - -(define_insn_reservation "future-crlogical" 2 - (and (eq_attr "type" "cr_logical") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") - -(define_insn_reservation "future-mfcrf" 2 - (and (eq_attr "type" "mfcrf") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") - -(define_insn_reservation "future-mfcr" 6 - (and (eq_attr "type" "mfcr") - (eq_attr "cpu" "future")) - "DU_C3_future,VSU_future") - -; Should differentiate between 1 cr field and > 1 since target of > 1 cr -; is cracked -(define_insn_reservation "future-mtcr" 2 - (and (eq_attr "type" "mtcr") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") - -; Move to LR/CTR are executed in VSU -(define_insn_reservation "future-mtjmpr" 5 - (and (eq_attr "type" "mtjmpr") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") - -; Floating point/Vector ops -(define_insn_reservation "future-fpsimple" 2 - (and (eq_attr "type" "fpsimple") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future") - -(define_insn_reservation "future-fp" 5 - (and (eq_attr "type" "fp,dmul") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future") - -(define_insn_reservation "future-fpcompare" 3 - (and (eq_attr "type" "fpcompare") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future") - -; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other -; div/sqrt insns, but for the most part do not block pipelined ops. -(define_insn_reservation "future-sdiv" 22 - (and (eq_attr "type" "sdiv") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future,FP_DIV_future") - -(define_insn_reservation "future-ddiv" 27 - (and (eq_attr "type" "ddiv") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future,FP_DIV_future") - -(define_insn_reservation "future-sqrt" 26 - (and (eq_attr "type" "ssqrt") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future,FP_DIV_future") - -(define_insn_reservation "future-dsqrt" 36 - (and (eq_attr "type" "dsqrt") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future,FP_DIV_future") - -(define_insn_reservation "future-vec-2cyc" 2 - (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_super_future") - -(define_insn_reservation "future-veccmp" 3 - (and (eq_attr "type" "veccmp") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_super_future") - -(define_insn_reservation "future-vecsimple" 3 - (and (eq_attr "type" "vecsimple") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_super_future") - -(define_insn_reservation "future-vecnormal" 7 - (and (eq_attr "type" "vecfloat,vecdouble") - (eq_attr "size" "!128") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_super_future") - -; Quad-precision FP ops, execute in DFU -(define_insn_reservation "future-qp" 12 - (and (eq_attr "type" "vecfloat,vecdouble") - (eq_attr "size" "128") - (eq_attr "cpu" "future")) - "DU_super_future,dfu_future") - -(define_insn_reservation "future-vecperm" 3 - (and (eq_attr "type" "vecperm") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_PRM_future") - -(define_insn_reservation "future-veccomplex" 7 - (and (eq_attr "type" "veccomplex") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_super_future") - -(define_insn_reservation "future-vecfdiv" 24 - (and (eq_attr "type" "vecfdiv") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_super_future,VEC_DIV_future") - -(define_insn_reservation "future-vecdiv" 27 - (and (eq_attr "type" "vecdiv") - (eq_attr "size" "!128") - (eq_attr "cpu" "future")) - "DU_super_future,VSU_super_future,VEC_DIV_future") - -; Use 8 for DFU reservation on QP div/mul to limit DFA state size -(define_insn_reservation "future-qpdiv" 56 - (and (eq_attr "type" "vecdiv") - (eq_attr "size" "128") - (eq_attr "cpu" "future")) - "DU_super_future,dfu_future*8") - -(define_insn_reservation "future-qpmul" 24 - (and (eq_attr "type" "qmul") - (eq_attr "size" "128") - (eq_attr "cpu" "future")) - "DU_super_future,dfu_future*8") - -(define_insn_reservation "future-mffgpr" 2 - (and (eq_attr "type" "mffgpr") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future") - -(define_insn_reservation "future-mftgpr" 2 - (and (eq_attr "type" "mftgpr") - (eq_attr "cpu" "future")) - "DU_slice_3_future,VSU_future") - - -; Branch Unit -; Move from LR/CTR are executed in BRU but consume a writeback port from an -; execution slice. -(define_insn_reservation "future-mfjmpr" 6 - (and (eq_attr "type" "mfjmpr") - (eq_attr "cpu" "future")) - "DU_branch_future,bru_future+VSU_future") - -; Branch is 2 cycles -(define_insn_reservation "future-branch" 2 - (and (eq_attr "type" "jmpreg,branch") - (eq_attr "cpu" "future")) - "DU_branch_future,bru_future") - - -; Crypto Unit -(define_insn_reservation "future-crypto" 6 - (and (eq_attr "type" "crypto") - (eq_attr "cpu" "future")) - "DU_super_future,cryptu_future") - - -; HTM Unit -(define_insn_reservation "future-htm" 4 - (and (eq_attr "type" "htm") - (eq_attr "cpu" "future")) - "DU_C2_future,LSU_future") - -(define_insn_reservation "future-htm-simple" 2 - (and (eq_attr "type" "htmsimple") - (eq_attr "cpu" "future")) - "DU_any_future,VSU_future") - - -; DFP Unit -(define_insn_reservation "future-dfp" 12 - (and (eq_attr "type" "dfp") - (eq_attr "cpu" "future")) - "DU_even_future,dfu_future") - diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 34776c8421e5..2ded33012827 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -641,9 +641,9 @@ extern int dot_symbols; #undef TARGET_FLOAT128_ENABLE_TYPE #define TARGET_FLOAT128_ENABLE_TYPE 1 -/* Enable using prefixed PC-relative addressing on the 'future' machine if the - ABI supports it. The ELF v2 ABI only supports PC-relative relocations for +/* Enable using prefixed PC-relative addressing on POWER10 if the ABI + supports it. The ELF v2 ABI only supports PC-relative relocations for the medium code model. */ -#define PCREL_SUPPORTED_BY_OS (TARGET_FUTURE && TARGET_PREFIXED \ +#define PCREL_SUPPORTED_BY_OS (TARGET_POWER10 && TARGET_PREFIXED \ && ELFv2_ABI_CHECK \ && TARGET_CMODEL == CMODEL_MEDIUM) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md new file mode 100644 index 000000000000..9f8a58257441 --- /dev/null +++ b/gcc/config/rs6000/power10.md @@ -0,0 +1,521 @@ +;; Scheduling description for IBM POWER10 processor. +;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; +;; This is a clone of power9.md. It is intended to be a placeholder until a +;; real scheduler model can be contributed. +;; The original power9.md was contributed by Pat Haugen (pthaugen@us.ibm.com). + +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; This file was cloned from power9.md, it does not (yet) describe the actual +;; POWER10 processor. + +(define_automaton "power10dsp,power10lsu,power10vsu,power10fpdiv,power10misc") + +(define_cpu_unit "lsu0_power10,lsu1_power10,lsu2_power10,lsu3_power10" "power10lsu") +(define_cpu_unit "vsu0_power10,vsu1_power10,vsu2_power10,vsu3_power10" "power10vsu") +; Two vector permute units, part of vsu +(define_cpu_unit "prm0_power10,prm1_power10" "power10vsu") +; Two fixed point divide units, not pipelined +(define_cpu_unit "fx_div0_power10,fx_div1_power10" "power10misc") +(define_cpu_unit "bru_power10,cryptu_power10,dfu_power10" "power10misc") +; Create a false unit for use by non-pipelined FP div/sqrt +(define_cpu_unit "fp_div0_power10,fp_div1_power10,fp_div2_power10,fp_div3_power10" + "power10fpdiv") + + +(define_cpu_unit "x0_power10,x1_power10,xa0_power10,xa1_power10, + x2_power10,x3_power10,xb0_power10,xb1_power10, + br0_power10,br1_power10" "power10dsp") + + +; Dispatch port reservations +; +; The processor can dispatch a maximum of 6 iops per cycle with the following +; general restrictions (other restrictions also apply): +; 1) At most 2 iops per execution slice +; 2) At most 2 iops to the branch unit +; Note that insn position in a dispatch group of 6 insns does not infer which +; execution slice the insn is routed to. The units are used to infer the +; conflicts that exist (i.e. an 'even' requirement will preclude dispatch +; with 2 insns with 'superslice' requirement). + +; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but +; are listed as separate units to allow those insns that preclude its use to +; still be scheduled two to a superslice while reserving the 3rd slot. The +; same applies for xb0/xb1. +(define_reservation "DU_xa_power10" "xa0_power10+xa1_power10") +(define_reservation "DU_xb_power10" "xb0_power10+xb1_power10") + +; Any execution slice dispatch +(define_reservation "DU_any_power10" + "x0_power10|x1_power10|DU_xa_power10|x2_power10|x3_power10| + DU_xb_power10") + +; Even slice, actually takes even/odd slots +(define_reservation "DU_even_power10" "x0_power10+x1_power10|x2_power10+x3_power10") + +; Slice plus 3rd slot +(define_reservation "DU_slice_3_power10" + "x0_power10+xa0_power10|x1_power10+xa1_power10| + x2_power10+xb0_power10|x3_power10+xb1_power10") + +; Superslice +(define_reservation "DU_super_power10" + "x0_power10+x1_power10|x2_power10+x3_power10") + +; 2-way cracked +(define_reservation "DU_C2_power10" "x0_power10+x1_power10| + x1_power10+DU_xa_power10| + x1_power10+x2_power10| + DU_xa_power10+x2_power10| + x2_power10+x3_power10| + x3_power10+DU_xb_power10") + +; 2-way cracked plus 3rd slot +(define_reservation "DU_C2_3_power10" "x0_power10+x1_power10+xa0_power10| + x1_power10+x2_power10+xa1_power10| + x2_power10+x3_power10+xb0_power10") + +; 3-way cracked (consumes whole decode/dispatch cycle) +(define_reservation "DU_C3_power10" + "x0_power10+x1_power10+xa0_power10+xa1_power10+x2_power10+ + x3_power10+xb0_power10+xb1_power10+br0_power10+br1_power10") + +; Branch ports +(define_reservation "DU_branch_power10" "br0_power10|br1_power10") + + +; Execution unit reservations +(define_reservation "LSU_power10" + "lsu0_power10|lsu1_power10|lsu2_power10|lsu3_power10") + +(define_reservation "LSU_pair_power10" + "lsu0_power10+lsu1_power10|lsu1_power10+lsu2_power10| + lsu2_power10+lsu3_power10|lsu3_power10+lsu0_power10") + +(define_reservation "VSU_power10" + "vsu0_power10|vsu1_power10|vsu2_power10|vsu3_power10") + +(define_reservation "VSU_super_power10" + "vsu0_power10+vsu1_power10|vsu2_power10+vsu3_power10") + +(define_reservation "VSU_PRM_power10" "prm0_power10|prm1_power10") + +; Define the reservation to be used by FP div/sqrt which allows other insns +; to be issued to the VSU, but blocks other div/sqrt for a number of cycles. +; Note that the number of cycles blocked varies depending on insn, but we +; just use the same number for all in order to keep the number of DFA states +; reasonable. +(define_reservation "FP_DIV_power10" + "fp_div0_power10*8|fp_div1_power10*8|fp_div2_power10*8| + fp_div3_power10*8") +(define_reservation "VEC_DIV_power10" + "fp_div0_power10*8+fp_div1_power10*8| + fp_div2_power10*8+fp_div3_power10*8") + + +; LS Unit +(define_insn_reservation "power10-load" 4 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "no") + (eq_attr "update" "no") + (eq_attr "cpu" "power10")) + "DU_any_power10,LSU_power10") + +(define_insn_reservation "power10-load-update" 4 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "no") + (eq_attr "update" "yes") + (eq_attr "cpu" "power10")) + "DU_C2_power10,LSU_power10+VSU_power10") + +(define_insn_reservation "power10-load-ext" 6 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "yes") + (eq_attr "update" "no") + (eq_attr "cpu" "power10")) + "DU_C2_power10,LSU_power10") + +(define_insn_reservation "power10-load-ext-update" 6 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "yes") + (eq_attr "update" "yes") + (eq_attr "cpu" "power10")) + "DU_C3_power10,LSU_power10+VSU_power10") + +(define_insn_reservation "power10-fpload-double" 4 + (and (eq_attr "type" "fpload") + (eq_attr "update" "no") + (eq_attr "size" "64") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,LSU_power10") + +(define_insn_reservation "power10-fpload-update-double" 4 + (and (eq_attr "type" "fpload") + (eq_attr "update" "yes") + (eq_attr "size" "64") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,LSU_power10+VSU_power10") + +; SFmode loads are cracked and have additional 2 cycles over DFmode +(define_insn_reservation "power10-fpload-single" 6 + (and (eq_attr "type" "fpload") + (eq_attr "update" "no") + (eq_attr "size" "32") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,LSU_power10") + +(define_insn_reservation "power10-fpload-update-single" 6 + (and (eq_attr "type" "fpload") + (eq_attr "update" "yes") + (eq_attr "size" "32") + (eq_attr "cpu" "power10")) + "DU_C3_power10,LSU_power10+VSU_power10") + +(define_insn_reservation "power10-vecload" 5 + (and (eq_attr "type" "vecload") + (eq_attr "cpu" "power10")) + "DU_any_power10,LSU_pair_power10") + +; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store +(define_insn_reservation "power10-store" 0 + (and (eq_attr "type" "store") + (eq_attr "update" "no") + (eq_attr "indexed" "no") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,LSU_power10") + +(define_insn_reservation "power10-store-indexed" 0 + (and (eq_attr "type" "store") + (eq_attr "update" "no") + (eq_attr "indexed" "yes") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,LSU_power10") + +; Update forms have 2 cycle latency for updated addr reg +(define_insn_reservation "power10-store-update" 2 + (and (eq_attr "type" "store") + (eq_attr "update" "yes") + (eq_attr "indexed" "no") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,LSU_power10+VSU_power10") + +; Update forms have 2 cycle latency for updated addr reg +(define_insn_reservation "power10-store-update-indexed" 2 + (and (eq_attr "type" "store") + (eq_attr "update" "yes") + (eq_attr "indexed" "yes") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,LSU_power10+VSU_power10") + +(define_insn_reservation "power10-fpstore" 0 + (and (eq_attr "type" "fpstore") + (eq_attr "update" "no") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,LSU_power10") + +; Update forms have 2 cycle latency for updated addr reg +(define_insn_reservation "power10-fpstore-update" 2 + (and (eq_attr "type" "fpstore") + (eq_attr "update" "yes") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,LSU_power10+VSU_power10") + +(define_insn_reservation "power10-vecstore" 0 + (and (eq_attr "type" "vecstore") + (eq_attr "cpu" "power10")) + "DU_super_power10,LSU_pair_power10") + +(define_insn_reservation "power10-larx" 4 + (and (eq_attr "type" "load_l") + (eq_attr "cpu" "power10")) + "DU_any_power10,LSU_power10") + +(define_insn_reservation "power10-stcx" 2 + (and (eq_attr "type" "store_c") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,LSU_power10+VSU_power10") + +(define_insn_reservation "power10-sync" 4 + (and (eq_attr "type" "sync,isync") + (eq_attr "cpu" "power10")) + "DU_any_power10,LSU_power10") + + +; VSU Execution Unit + +; Fixed point ops + +; Most ALU insns are simple 2 cycle, including record form +(define_insn_reservation "power10-alu" 2 + (and (eq_attr "type" "add,exts,integer,logical,isel") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") +; 5 cycle CR latency +(define_bypass 5 "power10-alu" + "power10-crlogical,power10-mfcr,power10-mfcrf") + +; Rotate/shift prevent use of third slot +(define_insn_reservation "power10-rot" 2 + (and (eq_attr "type" "insert,shift") + (eq_attr "dot" "no") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10") + +; Record form rotate/shift are cracked +(define_insn_reservation "power10-cracked-alu" 2 + (and (eq_attr "type" "insert,shift") + (eq_attr "dot" "yes") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,VSU_power10") +; 7 cycle CR latency +(define_bypass 7 "power10-cracked-alu" + "power10-crlogical,power10-mfcr,power10-mfcrf") + +(define_insn_reservation "power10-alu2" 3 + (and (eq_attr "type" "cntlz,popcnt,trap") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") +; 6 cycle CR latency +(define_bypass 6 "power10-alu2" + "power10-crlogical,power10-mfcr,power10-mfcrf") + +(define_insn_reservation "power10-cmp" 2 + (and (eq_attr "type" "cmp") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") + + +; Treat 'two' and 'three' types as 2 or 3 way cracked +(define_insn_reservation "power10-two" 4 + (and (eq_attr "type" "two") + (eq_attr "cpu" "power10")) + "DU_C2_power10,VSU_power10") + +(define_insn_reservation "power10-three" 6 + (and (eq_attr "type" "three") + (eq_attr "cpu" "power10")) + "DU_C3_power10,VSU_power10") + +(define_insn_reservation "power10-mul" 5 + (and (eq_attr "type" "mul") + (eq_attr "dot" "no") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10") + +(define_insn_reservation "power10-mul-compare" 5 + (and (eq_attr "type" "mul") + (eq_attr "dot" "yes") + (eq_attr "cpu" "power10")) + "DU_C2_3_power10,VSU_power10") +; 10 cycle CR latency +(define_bypass 10 "power10-mul-compare" + "power10-crlogical,power10-mfcr,power10-mfcrf") + +; Fixed point divides reserve the divide units for a minimum of 8 cycles +(define_insn_reservation "power10-idiv" 16 + (and (eq_attr "type" "div") + (eq_attr "size" "32") + (eq_attr "cpu" "power10")) + "DU_even_power10,fx_div0_power10*8|fx_div1_power10*8") + +(define_insn_reservation "power10-ldiv" 24 + (and (eq_attr "type" "div") + (eq_attr "size" "64") + (eq_attr "cpu" "power10")) + "DU_even_power10,fx_div0_power10*8|fx_div1_power10*8") + +(define_insn_reservation "power10-crlogical" 2 + (and (eq_attr "type" "cr_logical") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") + +(define_insn_reservation "power10-mfcrf" 2 + (and (eq_attr "type" "mfcrf") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") + +(define_insn_reservation "power10-mfcr" 6 + (and (eq_attr "type" "mfcr") + (eq_attr "cpu" "power10")) + "DU_C3_power10,VSU_power10") + +; Should differentiate between 1 cr field and > 1 since target of > 1 cr +; is cracked +(define_insn_reservation "power10-mtcr" 2 + (and (eq_attr "type" "mtcr") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") + +; Move to LR/CTR are executed in VSU +(define_insn_reservation "power10-mtjmpr" 5 + (and (eq_attr "type" "mtjmpr") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") + +; Floating point/Vector ops +(define_insn_reservation "power10-fpsimple" 2 + (and (eq_attr "type" "fpsimple") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10") + +(define_insn_reservation "power10-fp" 5 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10") + +(define_insn_reservation "power10-fpcompare" 3 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10") + +; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other +; div/sqrt insns, but for the most part do not block pipelined ops. +(define_insn_reservation "power10-sdiv" 22 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10,FP_DIV_power10") + +(define_insn_reservation "power10-ddiv" 27 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10,FP_DIV_power10") + +(define_insn_reservation "power10-sqrt" 26 + (and (eq_attr "type" "ssqrt") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10,FP_DIV_power10") + +(define_insn_reservation "power10-dsqrt" 36 + (and (eq_attr "type" "dsqrt") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10,FP_DIV_power10") + +(define_insn_reservation "power10-vec-2cyc" 2 + (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_super_power10") + +(define_insn_reservation "power10-veccmp" 3 + (and (eq_attr "type" "veccmp") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_super_power10") + +(define_insn_reservation "power10-vecsimple" 3 + (and (eq_attr "type" "vecsimple") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_super_power10") + +(define_insn_reservation "power10-vecnormal" 7 + (and (eq_attr "type" "vecfloat,vecdouble") + (eq_attr "size" "!128") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_super_power10") + +; Quad-precision FP ops, execute in DFU +(define_insn_reservation "power10-qp" 12 + (and (eq_attr "type" "vecfloat,vecdouble") + (eq_attr "size" "128") + (eq_attr "cpu" "power10")) + "DU_super_power10,dfu_power10") + +(define_insn_reservation "power10-vecperm" 3 + (and (eq_attr "type" "vecperm") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_PRM_power10") + +(define_insn_reservation "power10-veccomplex" 7 + (and (eq_attr "type" "veccomplex") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_super_power10") + +(define_insn_reservation "power10-vecfdiv" 24 + (and (eq_attr "type" "vecfdiv") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_super_power10,VEC_DIV_power10") + +(define_insn_reservation "power10-vecdiv" 27 + (and (eq_attr "type" "vecdiv") + (eq_attr "size" "!128") + (eq_attr "cpu" "power10")) + "DU_super_power10,VSU_super_power10,VEC_DIV_power10") + +; Use 8 for DFU reservation on QP div/mul to limit DFA state size +(define_insn_reservation "power10-qpdiv" 56 + (and (eq_attr "type" "vecdiv") + (eq_attr "size" "128") + (eq_attr "cpu" "power10")) + "DU_super_power10,dfu_power10*8") + +(define_insn_reservation "power10-qpmul" 24 + (and (eq_attr "type" "qmul") + (eq_attr "size" "128") + (eq_attr "cpu" "power10")) + "DU_super_power10,dfu_power10*8") + +(define_insn_reservation "power10-mffgpr" 2 + (and (eq_attr "type" "mffgpr") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10") + +(define_insn_reservation "power10-mftgpr" 2 + (and (eq_attr "type" "mftgpr") + (eq_attr "cpu" "power10")) + "DU_slice_3_power10,VSU_power10") + + +; Branch Unit +; Move from LR/CTR are executed in BRU but consume a writeback port from an +; execution slice. +(define_insn_reservation "power10-mfjmpr" 6 + (and (eq_attr "type" "mfjmpr") + (eq_attr "cpu" "power10")) + "DU_branch_power10,bru_power10+VSU_power10") + +; Branch is 2 cycles +(define_insn_reservation "power10-branch" 2 + (and (eq_attr "type" "jmpreg,branch") + (eq_attr "cpu" "power10")) + "DU_branch_power10,bru_power10") + + +; Crypto Unit +(define_insn_reservation "power10-crypto" 6 + (and (eq_attr "type" "crypto") + (eq_attr "cpu" "power10")) + "DU_super_power10,cryptu_power10") + + +; HTM Unit +(define_insn_reservation "power10-htm" 4 + (and (eq_attr "type" "htm") + (eq_attr "cpu" "power10")) + "DU_C2_power10,LSU_power10") + +(define_insn_reservation "power10-htm-simple" 2 + (and (eq_attr "type" "htmsimple") + (eq_attr "cpu" "power10")) + "DU_any_power10,VSU_power10") + + +; DFP Unit +(define_insn_reservation "power10-dfp" 12 + (and (eq_attr "type" "dfp") + (eq_attr "cpu" "power10")) + "DU_even_power10,dfu_power10") + diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 771f531e3564..b98fc27b406c 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2693,7 +2693,7 @@ BU_SPECIAL_X (RS6000_BUILTIN_CPU_SUPPORTS, "__builtin_cpu_supports", BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, RS6000_BTC_MISC) -/* FUTURE MMA builtins. */ +/* POWER10 MMA builtins. */ BU_VSX_1 (XVCVBF16SP, "xvcvbf16sp", MISC, vsx_xvcvbf16sp) BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index a7c210c6db16..e0ea0e748bde 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -10566,8 +10566,8 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode) "-m64"); else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC) error ("%qs requires the %qs option", name, "-mcpu=power9"); - else if ((fnmask & RS6000_BTM_FUTURE) != 0) - error ("%qs requires the %qs option", name, "-mcpu=future"); + else if ((fnmask & RS6000_BTM_P10) != 0) + error ("%qs requires the %qs option", name, "-mcpu=power10"); else if ((fnmask & RS6000_BTM_MMA) != 0) error ("%qs requires the %qs option", name, "-mmma"); else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 667c7ecefb84..8d2c1ffd6cf7 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -75,15 +75,14 @@ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_P9_VECTOR) -/* Flags that need to be turned off if -mno-future. */ -#define OTHER_FUTURE_MASKS (OPTION_MASK_MMA \ +/* Flags that need to be turned off if -mno-power10. */ +#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \ | OPTION_MASK_PCREL \ | OPTION_MASK_PREFIXED) -/* Support for a future processor's features. */ -#define ISA_FUTURE_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ - | OPTION_MASK_FUTURE \ - | OTHER_FUTURE_MASKS) +#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ + | OPTION_MASK_POWER10 \ + | OTHER_POWER10_MASKS) /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ @@ -129,7 +128,7 @@ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ - | OPTION_MASK_FUTURE \ + | OPTION_MASK_POWER10 \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ @@ -243,9 +242,8 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER) +RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 - | ISA_FUTURE_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index da901341b286..eaf6edc87546 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -61,8 +61,7 @@ enum processor_type PROCESSOR_POWER7, PROCESSOR_POWER8, PROCESSOR_POWER9, - - PROCESSOR_FUTURE, + PROCESSOR_POWER10, PROCESSOR_RS64A, PROCESSOR_MPCCORE, diff --git a/gcc/config/rs6000/rs6000-string.c b/gcc/config/rs6000/rs6000-string.c index fe7177f10fda..c35d93180ca1 100644 --- a/gcc/config/rs6000/rs6000-string.c +++ b/gcc/config/rs6000/rs6000-string.c @@ -963,7 +963,7 @@ expand_compare_loop (rtx operands[]) max_bytes = 64; break; case PROCESSOR_POWER9: - case PROCESSOR_FUTURE: + case PROCESSOR_POWER10: if (bytes_is_const) max_bytes = 191; else diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 0c4f89ead023..8ae2b6030bb5 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -183,17 +183,17 @@ EnumValue Enum(rs6000_cpu_opt_value) String(power9) Value(51) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc) Value(52) +Enum(rs6000_cpu_opt_value) String(power10) Value(52) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(53) +Enum(rs6000_cpu_opt_value) String(powerpc) Value(53) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(54) +Enum(rs6000_cpu_opt_value) String(powerpc64) Value(54) EnumValue -Enum(rs6000_cpu_opt_value) String(rs64) Value(55) +Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue -Enum(rs6000_cpu_opt_value) String(future) Value(56) +Enum(rs6000_cpu_opt_value) String(rs64) Value(56) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a98c8b2e154a..33579514bda6 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -259,7 +259,8 @@ enum { CLONE_ISA_2_05, /* ISA 2.05 (power6). */ CLONE_ISA_2_06, /* ISA 2.06 (power7). */ CLONE_ISA_2_07, /* ISA 2.07 (power8). */ - CLONE_ISA_3_00, /* ISA 3.00 (power9). */ + CLONE_ISA_3_00, /* ISA 3.0 (power9). */ + CLONE_ISA_3_1, /* ISA 3.1 (power10). */ CLONE_MAX }; @@ -274,7 +275,8 @@ static const struct clone_map rs6000_clone_map[CLONE_MAX] = { { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */ { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */ { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */ - { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */ + { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.0 (power9). */ + { OPTION_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */ }; @@ -3399,7 +3401,7 @@ rs6000_builtin_mask_calculate (void) | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0) | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0) | ((TARGET_MMA) ? RS6000_BTM_MMA : 0) - | ((TARGET_FUTURE) ? RS6000_BTM_FUTURE : 0)); + | ((TARGET_POWER10) ? RS6000_BTM_P10 : 0)); } /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered @@ -4092,15 +4094,15 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW; } - /* Enable -mprefixed by default on 'future' systems. */ - if (TARGET_FUTURE && (rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED) == 0) + /* Enable -mprefixed by default on power10 systems. */ + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED) == 0) rs6000_isa_flags |= OPTION_MASK_PREFIXED; - /* -mprefixed requires -mcpu=future. */ - else if (TARGET_PREFIXED && !TARGET_FUTURE) + /* -mprefixed requires -mcpu=power10 (or later). */ + else if (TARGET_PREFIXED && !TARGET_POWER10) { if ((rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED) != 0) - error ("%qs requires %qs", "-mprefixed", "-mcpu=future"); + error ("%qs requires %qs", "-mprefixed", "-mcpu=power10"); rs6000_isa_flags &= ~OPTION_MASK_PREFIXED; } @@ -4262,11 +4264,11 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_PCREL; } - /* Turn off vector pair/mma options on non-future systems. */ - if (!TARGET_FUTURE && TARGET_MMA) + /* Turn off vector pair/mma options on non-power10 systems. */ + if (!TARGET_POWER10 && TARGET_MMA) { if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) - error ("%qs requires %qs", "-mmma", "-mcpu=future"); + error ("%qs requires %qs", "-mmma", "-mcpu=power10"); rs6000_isa_flags &= ~OPTION_MASK_MMA; } @@ -4280,7 +4282,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER7 && rs6000_tune != PROCESSOR_POWER8 && rs6000_tune != PROCESSOR_POWER9 - && rs6000_tune != PROCESSOR_FUTURE + && rs6000_tune != PROCESSOR_POWER10 && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4294,7 +4296,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_FUTURE + || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4590,7 +4592,7 @@ rs6000_option_override_internal (bool global_init_p) break; case PROCESSOR_POWER9: - case PROCESSOR_FUTURE: + case PROCESSOR_POWER10: rs6000_cost = &power9_cost; break; @@ -5527,8 +5529,8 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT); - if ((flags & (ISA_FUTURE_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) - return "future"; + if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) + return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) return "power9"; if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0) @@ -8098,7 +8100,7 @@ avoiding_indexed_address_p (machine_mode mode) unsigned int msize = GET_MODE_SIZE (mode); /* Avoid indexed addressing for modes that have non-indexed load/store - instruction forms. On the future system, vector pairs have an indexed + instruction forms. On power10, vector pairs have an indexed form, but vector quads don't. */ if (msize > 16) return msize != 32; @@ -9186,7 +9188,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, { case PROCESSOR_POWER8: case PROCESSOR_POWER9: - case PROCESSOR_FUTURE: + case PROCESSOR_POWER10: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -17156,7 +17158,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_FUTURE) + || rs6000_tune == PROCESSOR_POWER10) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -17194,7 +17196,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_FUTURE + || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -17774,7 +17776,7 @@ rs6000_issue_rate (void) case PROCESSOR_POWER8: return 7; case PROCESSOR_POWER9: - case PROCESSOR_FUTURE: + case PROCESSOR_POWER10: return 6; default: return 1; @@ -21539,7 +21541,7 @@ rs6000_register_move_cost (machine_mode mode, allocation a move within the same class might turn out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_FUTURE) + || rs6000_tune == PROCESSOR_POWER10) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -23141,7 +23143,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, - { "future", OPTION_MASK_FUTURE, false, true }, + { "power10", OPTION_MASK_POWER10, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, @@ -23219,7 +23221,7 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { "float128", RS6000_BTM_FLOAT128, false, false }, { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false }, { "mma", RS6000_BTM_MMA, false, false }, - { "future", RS6000_BTM_FUTURE, false, false }, + { "power10", RS6000_BTM_P10, false, false }, }; /* Option variables that we want to support inside attribute((target)) and @@ -23908,7 +23910,7 @@ rs6000_disable_incompatible_switches (void) const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */ const char *const name; /* name of the switch. */ } flags[] = { - { OPTION_MASK_FUTURE, OTHER_FUTURE_MASKS, "future" }, + { OPTION_MASK_POWER10, OTHER_POWER10_MASKS, "power10" }, { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" }, { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" }, { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 8d9c435ca2ac..132ca20fd7d8 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -104,6 +104,7 @@ to the assembler if -mpower9-vector was also used. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ mcpu=power7: -mpower7; \ @@ -159,7 +160,6 @@ mcpu=e5500: -me5500; \ mcpu=e6500: -me6500; \ mcpu=titan: -mtitan; \ - mcpu=future: -mfuture; \ !mcpu*: %{mpower9-vector: -mpower9; \ mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ @@ -538,7 +538,7 @@ extern int rs6000_vector_align[]; #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN #define MASK_UPDATE OPTION_MASK_UPDATE #define MASK_VSX OPTION_MASK_VSX -#define MASK_FUTURE OPTION_MASK_FUTURE +#define MASK_POWER10 OPTION_MASK_POWER10 #ifndef IN_LIBGCC2 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 @@ -2321,7 +2321,7 @@ extern int frame_pointer_needed; #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ #define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ -#define RS6000_BTM_FUTURE MASK_FUTURE +#define RS6000_BTM_P10 MASK_POWER10 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ @@ -2344,7 +2344,7 @@ extern int frame_pointer_needed; | RS6000_BTM_FLOAT128 \ | RS6000_BTM_FLOAT128_HW \ | RS6000_BTM_MMA \ - | RS6000_BTM_FUTURE) + | RS6000_BTM_P10) /* Define builtin enum index. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 83e729a0e901..f199c8397512 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -312,7 +312,7 @@ ppc750,ppc7400,ppc7450, ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, - power4,power5,power6,power7,power8,power9,future, + power4,power5,power6,power7,power8,power9,power10, rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) @@ -359,7 +359,7 @@ (const_int 1) (and (eq_attr "isa" "fut") - (match_test "TARGET_FUTURE")) + (match_test "TARGET_POWER10")) (const_int 1) ] (const_int 0))) @@ -399,7 +399,7 @@ (include "power7.md") (include "power8.md") (include "power9.md") -(include "future.md") +(include "power10.md") (include "cell.md") (include "a2.md") (include "titan.md") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 92951483e4ec..6b426f2aaf19 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -567,9 +567,9 @@ long rs6000_stack_protector_guard_offset = 0 mspeculate-indirect-jumps Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save -mfuture -Target Report Mask(FUTURE) Var(rs6000_isa_flags) -Use instructions for a future architecture. +mpower10 +Target Report Mask(POWER10) Var(rs6000_isa_flags) +Use instructions added in ISA 3.1. mprefixed Target Report Mask(PREFIXED) Var(rs6000_isa_flags) diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index 81d550ce2368..1ddb5729cb28 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -73,7 +73,7 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \ $(srcdir)/config/rs6000/power7.md \ $(srcdir)/config/rs6000/power8.md \ $(srcdir)/config/rs6000/power9.md \ - $(srcdir)/config/rs6000/future.md \ + $(srcdir)/config/rs6000/power10.md \ $(srcdir)/config/rs6000/cell.md \ $(srcdir)/config/rs6000/a2.md \ $(srcdir)/config/rs6000/predicates.md \ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index b2abe219ebfa..cd4873ae4502 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5656,6 +5656,6 @@ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") (unspec:V16QI [(match_operand:V16QI 1 "vsx_register_operand" "wa")] XVCVBF16))] - "TARGET_FUTURE" + "TARGET_POWER10" " %x0,%x1" [(set_attr "type" "vecfloat")])