From: Julian Seward Date: Sun, 25 Feb 2007 17:13:19 +0000 (+0000) Subject: Comment-only change. X-Git-Tag: svn/VALGRIND_3_3_0~349 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9a4164c5f33a8ecbf5815978fefe7a3548784b12;p=thirdparty%2Fvalgrind.git Comment-only change. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@6617 --- diff --git a/coregrind/m_debuginfo/readdwarf.c b/coregrind/m_debuginfo/readdwarf.c index fad110745a..b0605d94c3 100644 --- a/coregrind/m_debuginfo/readdwarf.c +++ b/coregrind/m_debuginfo/readdwarf.c @@ -1470,7 +1470,7 @@ void ML_(read_debuginfo_dwarf1) ( the CFA]. JRS: on amd64, the dwarf register numbering is, as per - gdb-6.3/gdb/tdep-amd64.c and also amd64-abi-0.95.pdf: + gdb-6.3/gdb/tdep-amd64.c and also amd64-abi-0.98.pdf: 0 1 2 3 4 5 6 7 RAX RDX RCX RBX RSI RDI RBP RSP @@ -1479,9 +1479,31 @@ void ML_(read_debuginfo_dwarf1) ( R8 ... R15 16 is the return address (RIP) - - This is pretty strange given this not the encoding scheme for - registers used in amd64 code. + "The table defines Return Address to have a register number, + even though the address is stored in 0(%rsp) and not in a + physical register." + + 17 ... 24 + XMM0 ... XMM7 + + 25 ... 32 + XMM8 ... XMM15 + + 33 ... 40 + ST0 ... ST7 + + 41 ... 48 + MM0 ... MM7 + + 49 RFLAGS + 50,51,52,53,54,55 ES,CS,SS,DS,FS,GS + 58 FS.BASE (what's that?) + 59 GS.BASE (what's that?) + 62 TR (task register) + 63 LDTR (LDT register) + 64 MXCSR + 65 FCW (x87 control word) + 66 FSW (x86 status word) On x86 I cannot find any documentation. It _appears_ to be the actual instruction encoding, viz: