From: Julian Seward <jseward@acm.org>
Date: Mon, 18 Aug 2008 21:47:52 +0000 (+0000)
Subject: C89 fixes (stop gcc complaining).
X-Git-Tag: svn/VALGRIND_3_4_1^2~17
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9b2cabad372f6c39017feba6bf2fa8f096a1e21a;p=thirdparty%2Fvalgrind.git

C89 fixes (stop gcc complaining).


git-svn-id: svn://svn.valgrind.org/vex/trunk@1863
---

diff --git a/VEX/priv/guest-ppc/toIR.c b/VEX/priv/guest-ppc/toIR.c
index 1605a409d6..92d23d7eb8 100644
--- a/VEX/priv/guest-ppc/toIR.c
+++ b/VEX/priv/guest-ppc/toIR.c
@@ -8853,21 +8853,23 @@ static
 Bool dis_P6 ( UInt theInstr,
               Bool allow_F, Bool allow_V, Bool allow_FX, Bool allow_GX)
 {
-    /* This is a hack.  We should do P6 capability checking properly.
-       But anyway, make a guess at whether we should even try to handle
-       this instruction.  All P6 capable CPUs should be able to handle
-       F, V, FX and GX, so that seems like a good check. */
+   UInt opc, rd, ra, rb, opc2, dot;
+
+   /* This is a hack.  We should do P6 capability checking properly.
+      But anyway, make a guess at whether we should even try to handle
+      this instruction.  All P6 capable CPUs should be able to handle
+      F, V, FX and GX, so that seems like a good check. */
    if (! (allow_F && allow_V && allow_FX && allow_GX) )
       return False;
    if (!mode64)
       return False; /* only support P6 in 64-bit mode for now */
 
-   UInt opc  = ifieldOPC(theInstr);     /* primary opcode */
-   UInt rd   = ifieldRegDS(theInstr);   /* dst reg */
-   UInt ra   = ifieldRegA(theInstr);    /* first source reg */
-   UInt rb   = ifieldRegB(theInstr);    /* second source reg */
-   UInt opc2 = ifieldOPClo10(theInstr); /* secondary opc, 10:1 */
-   UInt dot  = ifieldBIT0(theInstr);    /* Rc field, bit 0 */
+   opc  = ifieldOPC(theInstr);     /* primary opcode */
+   rd   = ifieldRegDS(theInstr);   /* dst reg */
+   ra   = ifieldRegA(theInstr);    /* first source reg */
+   rb   = ifieldRegB(theInstr);    /* second source reg */
+   opc2 = ifieldOPClo10(theInstr); /* secondary opc, 10:1 */
+   dot  = ifieldBIT0(theInstr);    /* Rc field, bit 0 */
 
    if (opc == 63 && ra == 0/*presumably*/ && opc2 == 488) {
       /* frim (Floating Round to Integer Minus, PPC ISA 2.05 p137) */