From: Thomas Schwinge <thomas@codesourcery.com>
Date: Thu, 16 Nov 2023 22:17:36 +0000 (+0100)
Subject: GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases
X-Git-Tag: basepoints/gcc-15~4126
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0;p=thirdparty%2Fgcc.git

GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases

... added in commit ae0d2c240213c5a7f6959c032bfc9f0703cab787
"amdgcn: Add Accelerator VGPR registers".  This way, they're correctly tested
no matter what '-march=[...]' is used with 'make check'.

	gcc/testsuite/
	* gcc.target/gcn/avgpr-mem-double.c: Remove
	'dg-skip-if "incompatible ISA" [...]'.
	* gcc.target/gcn/avgpr-mem-int.c: Likewise.
	* gcc.target/gcn/avgpr-mem-long.c: Likewise.
	* gcc.target/gcn/avgpr-mem-short.c: Likewise.
	* gcc.target/gcn/avgpr-spill-double.c: Likewise.
	* gcc.target/gcn/avgpr-spill-int.c: Likewise.
	* gcc.target/gcn/avgpr-spill-long.c: Likewise.
	* gcc.target/gcn/avgpr-spill-short.c: Likewise.
---

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c
index ce089fb198d2..34317a507157 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c
index 03d814864664..5ea3755e1b8f 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c
index dcfb483f3f3c..b52fc98da85b 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c
index 91cc14ef181b..a3e4a8bf9a93 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
index 3e9996d3d102..53853a4b0757 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #define TYPE double
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
index 0b64c8ec176c..650f1587a1bb 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #ifndef TYPE
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
index 516890de14c7..51f887c4d59e 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #define TYPE long
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
index 1e556840e0f5..983d2017ff5f 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #define TYPE short