From: Angelo Dureghello Date: Wed, 10 Jun 2026 20:35:10 +0000 (+0200) Subject: m68k: mcf5441x: add CCR MISCCR2 bitfields X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9cacf00c83937db0af42d4e0271b5226b403838c;p=thirdparty%2Flinux.git m68k: mcf5441x: add CCR MISCCR2 bitfields Add CCR MISCCR2 register bitfields. Signed-off-by: Angelo Dureghello Signed-off-by: Greg Ungerer --- diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h index 9ce2cbb05316..ea01c7753b7b 100644 --- a/arch/m68k/include/asm/m5441xsim.h +++ b/arch/m68k/include/asm/m5441xsim.h @@ -8,6 +8,8 @@ #ifndef m5441xsim_h #define m5441xsim_h +#include + #define CPU_NAME "COLDFIRE(m5441x)" #define CPU_INSTR_PER_JIFFY 2 #define MCF_BUSCLK (MCF_CLK / 2) @@ -145,6 +147,21 @@ #define MCF_CCM_SBFCR 0xec090022 #define MCF_CCM_FNACR 0xec090024 +/* Bit definitions and macros for MCF_CCM_MISCCR2 */ +#define MCF_CCM_MISCCR2_ULPI BIT(0) +#define MCF_CCM_MISCCR2_FB_HALF BIT(1) +#define MCF_CCM_MISCCR2_ADC3_EN BIT(2) +#define MCF_CCM_MISCCR2_ADC7_EN BIT(3) +#define MCF_CCM_MISCCR2_ADC_EN BIT(4) +#define MCF_CCM_MISCCR2_DAC0_SEL BIT(5) +#define MCF_CCM_MISCCR2_DAC1_SEL BIT(6) +#define MCF_CCM_MISCCR2_DCC_BYP BIT(7) +#define MCF_CCM_MISCCR2_PLL_MODE GENMASK(10, 8) +#define MCF_CCM_MISCCR2_SWT_SCR BIT(12) +#define MCF_CCM_MISCCR2_RGPIO_HALF BIT(13) +#define MCF_CCM_MISCCR2_DDR2_CLK BIT(14) +#define MCF_CCM_MISCCR2_EXTCLK_BYP BIT(15) + /* * UART module. */