From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Tue, 9 Jun 2026 12:15:31 +0000 (+0200)
Subject: Merge tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux into soc/dt
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9cf333de20d20555d921018e34ae14da9bf5ae21;p=thirdparty%2Flinux.git

Merge tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux into soc/dt

RISC-V Devicetrees for v7.2

Sophgo:

For CV18xx serials:
- Add bindings for Milk-V "Duo S" board.

For SG2042:
- The CPU unit address incorrectly used decimal numbers,
  especially for those nodes which value >= 10. Now
  corrected to use hexadecimal.
- The MSI controller actually only supports 16 interrupts;
  corrected to match the actual situation.
- PCIe RCs are cache-coherent with the CPU. Marked it out
  for RC nodes.

For SG2044:
- The same as SG2042, use hex for CPU unit address.

In additional, update Chen Wang's email address for Sopgho
SoC maintainer.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux:
  riscv: dts: sophgo: reduce SG2042 MSI count to 16
  riscv: dts: sophgo: sg2042: use hex for CPU unit address
  riscv: dts: sophgo: sg2044: use hex for CPU unit address
  riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
  dt-bindings: soc: sophgo: add sg2000 plic and clint documentation
  dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles
  MAINTAINERS: update Chen Wang's email address

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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