From: Richard Henderson Date: Thu, 23 Dec 2004 01:31:17 +0000 (-0800) Subject: re PR target/19102 (-march=pentium3 breaks linux kernel compiles w/ gcc-3_4-branch... X-Git-Tag: releases/gcc-3.4.4~377 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9d0b72c9741573ebcd4c6ff6ff5f011da5e37148;p=thirdparty%2Fgcc.git re PR target/19102 (-march=pentium3 breaks linux kernel compiles w/ gcc-3_4-branch as of 2004/12/20) PR target/19102 * config/i386/i386.c (x86_inter_unit_moves): Disable. (ix86_hard_regno_mode_ok): Disallow SSE2 and MMX scalar modes in SSE registers when only SSE1 enabled. From-SVN: r92526 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 41f0f675897c..a51b849790d4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2004-12-22 Richard Henderson + + PR target/19102 + * config/i386/i386.c (x86_inter_unit_moves): Disable. + (ix86_hard_regno_mode_ok): Disallow SSE2 and MMX scalar modes + in SSE registers when only SSE1 enabled. + 2004-12-21 David O'Brien Backport from mainline: diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d1a56d2f5240..ff0c1617b4ce 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -522,7 +522,14 @@ const int x86_sse_typeless_stores = m_ATHLON_K8; const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4; const int x86_use_ffreep = m_ATHLON_K8; const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6; -const int x86_inter_unit_moves = ~(m_ATHLON_K8); + +/* ??? HACK! The following is a lie. SSE can hold e.g. SImode, and + indeed *must* be able to hold SImode so that SSE2 shifts are able + to work right. But this can result in some mighty surprising + register allocation when building kernels. Turning this off should + make us less likely to all-of-the-sudden select an SSE register. */ +const int x86_inter_unit_moves = 0; /* ~(m_ATHLON_K8) */ + const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_PPRO; /* In case the average insn count for single function invocation is @@ -14927,6 +14934,12 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) return VALID_FP_MODE_P (mode); if (SSE_REGNO_P (regno)) { + /* HACK! We didn't change all of the constraints for SSE1 for the + scalar modes on the branch. Fortunately, they're not required + for ABI compatibility. */ + if (!TARGET_SSE2 && !VECTOR_MODE_P (mode)) + return VALID_SSE_REG_MODE (mode); + /* We implement the move patterns for all vector modes into and out of SSE registers, even when no operation instructions are available. */