From: Jin Ma <jinma@linux.alibaba.com>
Date: Mon, 20 Jan 2025 16:29:30 +0000 (-0700)
Subject: RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov
X-Git-Tag: basepoints/gcc-16~2485
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9d869296f095a02c37d3721f546ce99663e5417c;p=thirdparty%2Fgcc.git

RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov

For XTheadCondMov, the bit width of rs2 should always be XLEN-sized, otherwise
the program logic will be wrong.

Reference form
https://github.com/XUANTIE-RV/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf

Synopsis
Move if equal zero.

Mnemonic
th.mveqz rd, rs1, rs2

Description
This instruction moves the content of register rs1 into rd if the content of rs2 is 0x0.
Otherwise, the value of rd does not change.

Operation
if (reg[rs2] == 0x0)
  reg[rd] := reg[rs1]

gcc/ChangeLog:

	* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>):
	Change GPR2 to X.
	(*th_cond_mov<GPR:mode>): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadcondmov-bug.c: New test.
---

diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 54b9737b430..d816f3b86dd 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -154,11 +154,11 @@
 
 ;; XTheadCondMov
 
-(define_insn "*th_cond_mov<GPR:mode><GPR2:mode>"
+(define_insn "*th_cond_mov<GPR:mode>"
   [(set (match_operand:GPR 0 "register_operand" "=r,r")
 	(if_then_else:GPR
 	 (match_operator 4 "equality_operator"
-		[(match_operand:GPR2 1 "register_operand" "r,r")
+		[(match_operand:X 1 "register_operand" "r,r")
 		 (const_int 0)])
 	 (match_operand:GPR 2 "reg_or_0_operand" "rJ,0")
 	 (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))]
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-bug.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-bug.c
new file mode 100644
index 00000000000..01cec629291
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-bug.c
@@ -0,0 +1,12 @@
+/* { dg-do compile  { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64d -O2" } */
+
+long long int
+foo (long long int x, long long int y)
+{
+  if (((int) x | (int) y) != 0)
+    return 6;
+  return x + y;
+}
+
+/* { dg-final { scan-assembler-times {\msext\.w\M} 1 } } */