From: Palmer Dabbelt Date: Wed, 1 Feb 2023 07:30:07 +0000 (-0800) Subject: Merge patch series "riscv: improve boot time isa extensions handling" X-Git-Tag: v6.3-rc1~86^2~22 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9daca9a5b9ac35361ce2d8d5ec10b19b7048d6cd;p=thirdparty%2Fkernel%2Flinux.git Merge patch series "riscv: improve boot time isa extensions handling" Jisheng Zhang says: Generally, riscv ISA extensions are fixed for any specific hardware platform, so a hart's features won't change after booting, this chacteristic makes it straightforward to use a static branch to check a specific ISA extension is supported or not to optimize performance. However, some ISA extensions such as SVPBMT and ZICBOM are handled via. the alternative sequences. Basically, for ease of maintenance, we prefer to use static branches in C code, but recently, Samuel found that the static branch usage in cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As Samuel pointed out, "Having a static branch in cpu_relax() is problematic because that function is widely inlined, including in some quite complex functions like in the VDSO. A quick measurement shows this static branch is responsible by itself for around 40% of the jump table." Samuel's findings pointed out one of a few downsides of static branches usage in C code to handle ISA extensions detected at boot time: static branch's metadata in the __jump_table section, which is not discarded after ISA extensions are finalized, wastes some space. I want to try to solve the issue for all possible dynamic handling of ISA extensions at boot time. Inspired by Mark[2], this patch introduces riscv_has_extension_*() helpers, which work like static branches but are patched using alternatives, thus the metadata can be freed after patching. [1]https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/ [2]https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/ [3]https://lore.kernel.org/linux-riscv/20221130225614.1594256-1-heiko@sntech.de/ * b4-shazam-merge: riscv: remove riscv_isa_ext_keys[] array and related usage riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() riscv: cpu_relax: switch to riscv_has_extension_likely() riscv: alternative: patch alternatives in the vDSO riscv: switch to relative alternative entries riscv: module: Add ADD16 and SUB16 rela types riscv: module: move find_section to module.h riscv: fpu: switch has_fpu() to riscv_has_extension_likely() riscv: introduce riscv_has_extension_[un]likely() riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions riscv: hwcap: make ISA extension ids can be used in asm riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier riscv: move riscv_noncoherent_supported() out of ZICBOM probe Link: https://lore.kernel.org/r/20230128172856.3814-1-jszhang@kernel.org Signed-off-by: Palmer Dabbelt --- 9daca9a5b9ac35361ce2d8d5ec10b19b7048d6cd diff --cc arch/riscv/include/asm/hwcap.h index 462d6cde9bac6,7936ae6f7bdfb..ee9c80fe0062c --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@@ -53,31 -40,27 +40,30 @@@ * available logical extension id. * Entries are sorted alphabetically. */ - enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SSTC, - RISCV_ISA_EXT_SVINVAL, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZBB, - RISCV_ISA_EXT_ZICBOM, - RISCV_ISA_EXT_ZIHINTPAUSE, - RISCV_ISA_EXT_ID_MAX - }; - static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); -#define RISCV_ISA_EXT_SSCOFPMF 26 -#define RISCV_ISA_EXT_SSTC 27 -#define RISCV_ISA_EXT_SVINVAL 28 -#define RISCV_ISA_EXT_SVPBMT 29 -#define RISCV_ISA_EXT_ZICBOM 30 -#define RISCV_ISA_EXT_ZIHINTPAUSE 31 ++#define RISCV_ISA_EXT_SSCOFPMF 26 ++#define RISCV_ISA_EXT_SSTC 27 ++#define RISCV_ISA_EXT_SVINVAL 28 ++#define RISCV_ISA_EXT_SVPBMT 29 ++#define RISCV_ISA_EXT_ZBB 30 ++#define RISCV_ISA_EXT_ZICBOM 31 ++#define RISCV_ISA_EXT_ZIHINTPAUSE 32 + + #ifndef __ASSEMBLY__ ++ + #include + /* - * This enum represents the logical ID for each RISC-V ISA extension static - * keys. We can use static key to optimize code path if some ISA extensions - * are available. - * Entries are sorted alphabetically. + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. */ - enum riscv_isa_ext_key { - RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ - RISCV_ISA_EXT_KEY_SVINVAL, - RISCV_ISA_EXT_KEY_ZIHINTPAUSE, - RISCV_ISA_EXT_KEY_MAX, + #define ELF_HWCAP (elf_hwcap) + + enum { + CAP_HWCAP = 1, }; + extern unsigned long elf_hwcap; + struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];