From: Rafał Hibner Date: Mon, 20 Apr 2026 07:46:40 +0000 (+0000) Subject: net: zynq_gem: Clear stale speed bits in NWCFG before setting new ones X-Git-Tag: v2026.07-rc1~20^2 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9e0511261221b63458bc0d4cfd08596f5c8840d4;p=thirdparty%2Fu-boot.git net: zynq_gem: Clear stale speed bits in NWCFG before setting new ones Commit ecba4380ad26 ("net: zynq_gem: Update the MDC clock divisor in the probe function") changed zynq_gem_init() from a direct register write to a read-modify-write pattern in order to preserve MDC clock divider bits. However, the old speed selection bits (SPEED100/SPEED1000) are never cleared before OR-ing in the new value. When the PHY renegotiates at a different speed between successive calls to zynq_gem_init() (e.g. link flapping from 1 Gbps to 100 Mbps on a marginal cable), both SPEED100 and SPEED1000 end up set simultaneously in NWCFG. This confuses the GEM hardware and no frames are received. Fix by explicitly clearing both speed bits before merging the new configuration, so only the currently negotiated speed is ever active. Fixes: ecba4380ad26 ("net: zynq_gem: Update the MDC clock divisor in the probe function") Signed-off-by: Rafał Hibner Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260420074640.4036119-1-rafal.hibner@secom.com.pl --- diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index e3f9fd72d2f..f570ae9ee73 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -631,6 +631,7 @@ static int zynq_gem_init(struct udevice *dev) break; } nwcfg = readl(®s->nwcfg); + nwcfg &= ~(ZYNQ_GEM_NWCFG_SPEED100 | ZYNQ_GEM_NWCFG_SPEED1000); nwcfg |= nwconfig; if (nwcfg) writel(nwcfg, ®s->nwcfg);