From: Ryan Chen Date: Fri, 12 Jun 2026 08:33:27 +0000 (+0930) Subject: arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9e84fd546dc3f9f97bfbf2717c2d71d878a4f46f;p=thirdparty%2Flinux.git arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme A report from shashiko-bot highlighted some concerns concurrent to application of the series[1]. Fix duplicate pinctrl_tach{0-15} and pinctrl_n{cts,dcd,dsr,ri}5 labels in aspeed-g7-soc1-pinctrl.dtsi. These didn't cause errors from dtc because dtc accepts duplicate labels for duplicate nodes specified through a node reference[2]. Drop the cpu-index from secondary/tertiary container nodes: reduce the "#address-cells" from 2 to 1 and update unit-addresses and reg accordingly. The 2-cell scheme was proposed in an early mailing list sketch to prompt discussion[3], but the design evolved in ways that made it unnecessary. Also remove URL comments from the DTS. The links were to comments in the kernel sources with discussion justifying the approach, but are not necessary to carry forward. [arj: Extend discussion in the commit message] Link: https://lore.kernel.org/all/20260609025708.ADBFE1F00893@smtp.kernel.org/ [1] Link: https://lore.kernel.org/all/b226339bb2abe42ce23e90eadbc654b426131083.camel@codeconstruct.com.au/ [2] Link: https://lore.kernel.org/all/1a2ca78746e00c2ec4bfc2953a897c48376ed36f.camel@codeconstruct.com.au/ [3] Suggested-by: Andrew Jeffery Fixes: e77bb5dc5759 ("arm64: dts: aspeed: Add initial AST27xx SoC device tree") Signed-off-by: Ryan Chen Link: https://patch.msgid.link/20260611-dtsi_fix-v1-1-ef2b7cd86d6d@aspeedtech.com Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20260612-aspeed-arm64-dt-v1-1-d1d1a4737905@codeconstruct.com.au Signed-off-by: Arnd Bergmann --- diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi index ef283d95649a..58193c3c3696 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-a35.dtsi @@ -84,32 +84,30 @@ }; secondary { - #address-cells = <2>; - /* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/of/address.c?h=v6.16#n491 */ + #address-cells = <1>; #size-cells = <0>; - /* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/of/address.c?h=v6.16#n430 */ - ssp_nvic: interrupt-controller@1,e000e100 { + ssp_nvic: interrupt-controller@e000e100 { compatible = "arm,v7m-nvic"; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; - reg = <1 0xe000e100>; + reg = <0xe000e100>; arm,num-irq-priority-bits = <3>; status = "disabled"; }; }; tertiary { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; - tsp_nvic: interrupt-controller@2,e000e100 { + tsp_nvic: interrupt-controller@e000e100 { compatible = "arm,v7m-nvic"; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; - reg = <2 0xe000e100>; + reg = <0xe000e100>; arm,num-irq-priority-bits = <3>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi index 72d93323593d..6edf14617b09 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1-pinctrl.dtsi @@ -496,87 +496,6 @@ function = "I3C15"; groups = "HVI3C15"; }; - - pinctrl_tach0_default: tach0-default-state { - function = "TACH0"; - groups = "TACH0"; - }; - - pinctrl_tach1_default: tach1-default-state { - function = "TACH1"; - groups = "TACH1"; - }; - - pinctrl_tach2_default: tach2-default-state { - function = "TACH2"; - groups = "TACH2"; - }; - - pinctrl_tach3_default: tach3-default-state { - function = "TACH3"; - groups = "TACH3"; - }; - - pinctrl_tach4_default: tach4-default-state { - function = "TACH4"; - groups = "TACH4"; - }; - - pinctrl_tach5_default: tach5-default-state { - function = "TACH5"; - groups = "TACH5"; - }; - - pinctrl_tach6_default: tach6-default-state { - function = "TACH6"; - groups = "TACH6"; - }; - - pinctrl_tach7_default: tach7-default-state { - function = "TACH7"; - groups = "TACH7"; - }; - - pinctrl_tach8_default: tach8-default-state { - function = "TACH8"; - groups = "TACH8"; - }; - - pinctrl_tach9_default: tach9-default-state { - function = "TACH9"; - groups = "TACH9"; - }; - - pinctrl_tach10_default: tach10-default-state { - function = "TACH10"; - groups = "TACH10"; - }; - - pinctrl_tach11_default: tach11-default-state { - function = "TACH11"; - groups = "TACH11"; - }; - - pinctrl_tach12_default: tach12-default-state { - function = "TACH12"; - groups = "TACH12"; - }; - - pinctrl_tach13_default: tach13-default-state { - function = "TACH13"; - groups = "TACH13"; - }; - - pinctrl_tach14_default: tach14-default-state { - function = "TACH14"; - groups = "TACH14"; - }; - - pinctrl_tach15_default: tach15-default-state { - function = "TACH15"; - groups = "TACH15"; - }; - pinctrl_thru0_default: thru0-default-state { function = "THRU0"; groups = "THRU0"; @@ -940,27 +859,6 @@ function = "UART3"; groups = "UART3"; }; - - pinctrl_ncts5_default: ncts5-default-state { - function = "NCTS5"; - groups = "NCTS5"; - }; - - pinctrl_ndcd5_default: ndcd5-default-state { - function = "NDCD5"; - groups = "NDCD5"; - }; - - pinctrl_ndsr5_default: ndsr5-default-state { - function = "NDSR5"; - groups = "NDSR5"; - }; - - pinctrl_nri5_default: nri5-default-state { - function = "NRI5"; - groups = "NRI5"; - }; - pinctrl_ndtr5_default: ndtr5-default-state { function = "NDTR5"; groups = "NDTR5";