From: Thomas Perrot Date: Thu, 8 Jan 2026 10:16:09 +0000 (+0100) Subject: opensbi: bump to 1.8 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9e85e2b427475c8c371acb1a7f293767af3324b4;p=thirdparty%2Fopenembedded%2Fopenembedded-core.git opensbi: bump to 1.8 This release has: - Safe and reverse list iteration - Stack protector support - Allocate heap housekeeping nodes dynamically - IPI device ratings - Andes QiLai SoC support - SpacemiT K1 SoC support - ESWIN Computing EIC7700 SoC support - Moved Ariane and Openpiton to generic platform - SiFive CLINT v2 support - Simple FDT based cache library - SiFive PL2 cache controller driver - SiFive Extensible Cache (EC) driver - SiFive TMC0 based HSM driver - SiFive SMC0 based system suspend driver - MPXY RPMI mailbox driver for voltage service group - MPXY RPMI mailbox driver for device power service group - MPXY RPMI mailbox driver for performance service group - HART protection abstraction Overall, this release has various domain related improvements and also adds multiple platform support. Additionally, enable PMP support on QEMU using rva23s64, as PMP is disabled by default, which causes the hart isolation configuration to fail [1]. [1] https://lists.nongnu.org/archive/html/qemu-riscv/2026-01/msg00048.html Signed-off-by: Thomas Perrot Signed-off-by: Mathieu Dubois-Briand Signed-off-by: Richard Purdie --- diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc index b755d32c9d..bac376ce5a 100644 --- a/meta/conf/machine/include/riscv/qemuriscv.inc +++ b/meta/conf/machine/include/riscv/qemuriscv.inc @@ -27,7 +27,7 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000" # qemuboot options QB_SMP ?= "-smp 4" QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi" -QB_CPU:riscv64 ?= "-cpu rva23s64" +QB_CPU:riscv64 ?= "-cpu rva23s64,pmp=true" QB_MACHINE = "-machine virt" QB_DEFAULT_BIOS = "fw_jump.elf" QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no" diff --git a/meta/recipes-bsp/opensbi/opensbi_1.7.bb b/meta/recipes-bsp/opensbi/opensbi_1.8.bb similarity index 96% rename from meta/recipes-bsp/opensbi/opensbi_1.7.bb rename to meta/recipes-bsp/opensbi/opensbi_1.8.bb index a460062e93..5352c01d66 100644 --- a/meta/recipes-bsp/opensbi/opensbi_1.7.bb +++ b/meta/recipes-bsp/opensbi/opensbi_1.8.bb @@ -8,8 +8,8 @@ require opensbi-payloads.inc inherit deploy -SRCREV = "a32a91069119e7a5aa31e6bc51d5e00860be3d80" -SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https" +SRCREV = "e7fa66c2160ec139de1853a00f669c09320a9256" +SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https;tag=v${PV}" TARGET_DBGSRC_DIR = "/share/opensbi/*/generic/firmware/"