From: Lad Prabhakar Date: Thu, 19 Mar 2026 14:15:14 +0000 (+0000) Subject: dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9efe63b74e9c30777db9815dc5d38d667576ac6f;p=thirdparty%2Fkernel%2Fstable.git dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties Document the pin configuration properties supported by the RZ/T2H pinctrl driver. The RZ/T2H SoC allows configuring several electrical characteristics through the DRCTLm (I/O Buffer Function Switching) registers. These registers control drive strength, bias configuration, Schmitt trigger input, and output slew rate. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260319141515.2053556-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml index f049013a4e0c9..63993b20524f5 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml @@ -83,6 +83,23 @@ definitions: input: true input-enable: true output-enable: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + slew-rate: + description: 0 is slow slew rate, 1 is fast slew rate + enum: [0, 1] + drive-strength-microamp: + description: | + Four discrete levels are supported (via registers DRCTLm), corresponding + to the following nominal values: + - 2500 (Low strength) + - 5000 (Middle strength) + - 9000 (High strength) + - 11800 (Ultra High strength) + enum: [2500, 5000, 9000, 11800] oneOf: - required: [pinmux] - required: [pins]