From: Philippe Waroquiers <philippe.waroquiers@skynet.be>
Date: Thu, 18 Jun 2015 21:31:32 +0000 (+0000)
Subject: * x86: on an SSE2 only host, Valgrind in 32 bits now claims to be a Pentium 4.
X-Git-Tag: svn/VALGRIND_3_11_0^2~37
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9f18ca9845c84fd07ed589bf0a117e782f34f236;p=thirdparty%2Fvalgrind.git

* x86: on an SSE2 only host, Valgrind in 32 bits now claims to be a Pentium 4.
       3.10.1 was wrongly claiming to be a CORE 2, which is SSSE3.



git-svn-id: svn://svn.valgrind.org/vex/trunk@3154
---

diff --git a/VEX/priv/guest_x86_defs.h b/VEX/priv/guest_x86_defs.h
index 0b5a1a6412..7b43c0ada9 100644
--- a/VEX/priv/guest_x86_defs.h
+++ b/VEX/priv/guest_x86_defs.h
@@ -147,6 +147,7 @@ extern void  x86g_dirtyhelper_storeF80le ( Addr, ULong );
 extern void  x86g_dirtyhelper_CPUID_sse0 ( VexGuestX86State* );
 extern void  x86g_dirtyhelper_CPUID_mmxext ( VexGuestX86State* );
 extern void  x86g_dirtyhelper_CPUID_sse1 ( VexGuestX86State* );
+extern void  x86g_dirtyhelper_CPUID_sse2 ( VexGuestX86State* );
 extern void  x86g_dirtyhelper_CPUID_sse3 ( VexGuestX86State* );
 
 extern void  x86g_dirtyhelper_FINIT ( VexGuestX86State* );
diff --git a/VEX/priv/guest_x86_helpers.c b/VEX/priv/guest_x86_helpers.c
index 035d229778..a3d6a84fe7 100644
--- a/VEX/priv/guest_x86_helpers.c
+++ b/VEX/priv/guest_x86_helpers.c
@@ -2297,6 +2297,46 @@ void x86g_dirtyhelper_CPUID_sse1 ( VexGuestX86State* st )
    }
 }
 
+/* Claim to be the following SSE2-capable CPU:
+   vendor_id    : GenuineIntel
+   cpu family   : 15
+   model        : 2
+   model name   : Intel(R) Pentium(R) 4 CPU 3.00GHz
+   stepping     : 9
+   microcode    : 0x17
+   cpu MHz      : 2992.577
+   cache size   : 512 KB
+   flags        : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
+                  pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe
+                   pebs bts cid xtpr
+   clflush size : 64
+   cache_alignment : 128
+   address sizes : 36 bits physical, 32 bits virtual
+*/
+void x86g_dirtyhelper_CPUID_sse2 ( VexGuestX86State* st )
+{
+   switch (st->guest_EAX) {
+      case 0: 
+         st->guest_EAX = 0x00000002;
+         st->guest_EBX = 0x756e6547;
+         st->guest_ECX = 0x6c65746e;
+         st->guest_EDX = 0x49656e69;
+         break;
+      case 1: 
+         st->guest_EAX = 0x00000f29;
+         st->guest_EBX = 0x01020809;
+         st->guest_ECX = 0x00004400;
+         st->guest_EDX = 0xbfebfbff;
+         break;
+      default:
+         st->guest_EAX = 0x03020101;
+         st->guest_EBX = 0x00000000;
+         st->guest_ECX = 0x00000000;
+         st->guest_EDX = 0x0c040883;
+         break;
+   }
+}
+
 /* Claim to be the following SSSE3-capable CPU (2 x ...):
    vendor_id       : GenuineIntel
    cpu family      : 6
diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c
index bcddea5b59..24bbd7f8fd 100644
--- a/VEX/priv/guest_x86_toIR.c
+++ b/VEX/priv/guest_x86_toIR.c
@@ -14847,6 +14847,11 @@ DisResult disInstr_X86_WRK (
             fAddr = &x86g_dirtyhelper_CPUID_sse3; 
          } 
          else
+         if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2) {
+            fName = "x86g_dirtyhelper_CPUID_sse2";
+            fAddr = &x86g_dirtyhelper_CPUID_sse2; 
+         } 
+         else
          if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE1) {
             fName = "x86g_dirtyhelper_CPUID_sse1";
             fAddr = &x86g_dirtyhelper_CPUID_sse1;