From: Rustam Adilov Date: Sun, 3 May 2026 09:35:25 +0000 (+0500) Subject: realtek: arch: rtl-otto: change to __raw reads and writes X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a03e379f5ae0cb75fdd45f6318e00caa54f63449;p=thirdparty%2Fopenwrt.git realtek: arch: rtl-otto: change to __raw reads and writes The realtek target uses the readl and writel for register access to switchcore and SoC bases. This works but if at some point the target wants to enable CONFIG_SWAP_IO_SPACE, the register access breaks as readl/writel would be operating in little endian as opposed to native. Fix it by replacing the readl/writel used in register access macros to a __raw variant which aligns with what upstream use for native endian access to registers. Signed-off-by: Rustam Adilov Link: https://github.com/openwrt/openwrt/pull/23206 Signed-off-by: Markus Stockhausen --- diff --git a/target/linux/realtek/files-6.18/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h b/target/linux/realtek/files-6.18/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h index 9079ff24f67..60178f076fc 100644 --- a/target/linux/realtek/files-6.18/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h +++ b/target/linux/realtek/files-6.18/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h @@ -15,8 +15,8 @@ #define RTL838X_SW_BASE ((volatile void *) 0xBB000000) -#define sw_r32(reg) readl(RTL838X_SW_BASE + reg) -#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg) +#define sw_r32(reg) __raw_readl(RTL838X_SW_BASE + reg) +#define sw_w32(val, reg) __raw_writel(val, RTL838X_SW_BASE + reg) #define sw_w32_mask(clear, set, reg) sw_w32((sw_r32(reg) & ~(clear)) | (set), reg) #define RTL838X_MODEL_NAME_INFO (0x00D4) diff --git a/target/linux/realtek/files-6.18/arch/mips/rtl-otto/prom.c b/target/linux/realtek/files-6.18/arch/mips/rtl-otto/prom.c index 7e2cf729e2b..3e59253f87a 100644 --- a/target/linux/realtek/files-6.18/arch/mips/rtl-otto/prom.c +++ b/target/linux/realtek/files-6.18/arch/mips/rtl-otto/prom.c @@ -35,8 +35,8 @@ #define RTL931X_DRAM_CONFIG 0x14304c -#define soc_r32(reg) readl(RTL_SOC_BASE + reg) -#define soc_w32(val, reg) writel(val, RTL_SOC_BASE + reg) +#define soc_r32(reg) __raw_readl(RTL_SOC_BASE + reg) +#define soc_w32(val, reg) __raw_writel(val, RTL_SOC_BASE + reg) struct rtl83xx_soc_info soc_info; EXPORT_SYMBOL(soc_info);