From: Julian Seward <jseward@acm.org>
Date: Mon, 4 Jan 2021 14:16:41 +0000 (+0100)
Subject: arm64 isel: in a couple places, use `xzr` as a source rather than loading zero into... 
X-Git-Tag: VALGRIND_3_17_0~80
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a0b559c224bcc9b6df2668ae6cfe2695f517d33d;p=thirdparty%2Fvalgrind.git

arm64 isel: in a couple places, use `xzr` as a source rather than loading zero into a reg.

Reduces code size by 0.27% for /usr/bin/date.
---

diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c
index 67dd06c78a..526da570a5 100644
--- a/VEX/priv/host_arm64_defs.c
+++ b/VEX/priv/host_arm64_defs.c
@@ -3955,9 +3955,9 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
          /* 100 1101 0100 mm cond 00 nn dd = CSEL Xd, Xn, Xm, cond */
          UInt dd   = iregEnc(i->ARM64in.CSel.dst);
          UInt nn   = iregEnc(i->ARM64in.CSel.argL);
-         UInt mm   = iregEnc(i->ARM64in.CSel.argR);
+         UInt mm   = iregEncOr31(i->ARM64in.CSel.argR); // Can be XZR
          UInt cond = (UInt)i->ARM64in.CSel.cond;
-         vassert(dd < 31 && nn < 31 && mm < 31 && cond < 16);
+         vassert(dd < 31 && nn < 31 && mm <= 31 && cond < 16);
          *p++ = X_3_8_5_6_5_5(X100, X11010100, mm, cond << 2, nn, dd);
          goto done;
       }
diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c
index d76973507b..1b8ad20a5a 100644
--- a/VEX/priv/host_arm64_isel.c
+++ b/VEX/priv/host_arm64_isel.c
@@ -2085,11 +2085,10 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
          case Iop_1Sto32:
          case Iop_1Sto64: {
             /* As with the iselStmt case for 'tmp:I1 = expr', we could
-               do a lot better here if it ever became necessary. */
-            HReg zero = newVRegI(env);
+               do a lot better here if it ever became necessary.  (CSDEC?) */
+            HReg zero = hregARM64_XZR_XSP(); // XZR in this context
             HReg one  = newVRegI(env);
             HReg dst  = newVRegI(env);
-            addInstr(env, ARM64Instr_Imm64(zero, 0));
             addInstr(env, ARM64Instr_Imm64(one,  1));
             ARM64CondCode cc = iselCondCode_C(env, e->Iex.Unop.arg);
             addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
@@ -2159,9 +2158,8 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
                addInstr(env, ARM64Instr_Logic(dst, src, one, ARM64lo_AND));
             } else {
                /* CLONE-01 */
-               HReg zero = newVRegI(env);
+               HReg zero = hregARM64_XZR_XSP(); // XZR in this context
                HReg one  = newVRegI(env);
-               addInstr(env, ARM64Instr_Imm64(zero, 0));
                addInstr(env, ARM64Instr_Imm64(one,  1));
                ARM64CondCode cc = iselCondCode_C(env, e->Iex.Unop.arg);
                addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
@@ -3985,10 +3983,9 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
             in that case.  Also, could do this just with a single CINC
             insn. */
          /* CLONE-01 */
-         HReg zero = newVRegI(env);
+         HReg zero = hregARM64_XZR_XSP(); // XZR in this context
          HReg one  = newVRegI(env);
          HReg dst  = lookupIRTemp(env, tmp);
-         addInstr(env, ARM64Instr_Imm64(zero, 0));
          addInstr(env, ARM64Instr_Imm64(one,  1));
          ARM64CondCode cc = iselCondCode_C(env, stmt->Ist.WrTmp.data);
          addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));