From: Richard Sandiford Date: Sat, 6 Jul 2019 08:26:33 +0000 (+0000) Subject: [i386] Fix ambiguous .md attribute uses X-Git-Tag: misc/cutover-git~4232 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a0cb70b7ea2b522f02a2384fbe1103d69904f916;p=thirdparty%2Fgcc.git [i386] Fix ambiguous .md attribute uses This patch is part of a series that fixes ambiguous attribute uses in .md files, i.e. cases in which attributes didn't use to specify an iterator, and in which could have different values depending on the iterator chosen. No behavioural change except for dropping the unused *andnot3_bcst permutations. 2019-07-06 Richard Sandiford gcc/ * config/i386/i386.md (*fop__3_i387) (l2): Fix ambiguous uses of .md attributes. * config/i386/sse.md (*avx512pf_gatherpfsf_mask) (*avx512pf_gatherpfdf_mask, *avx512pf_scatterpfsf_mask) (*avx512pf_scatterpfdf_mask, *avx2_gathersi) (*avx2_gathersi_2, *avx2_gatherdi) (*avx2_gatherdi_2, *avx2_gatherdi_3): Likewise. (*avx2_gatherdi_4, *avx512f_gathersi): Likewise. (*avx512f_gathersi_2, *avx512f_gatherdi): Likewise. (*avx512f_gatherdi_2, *avx512f_scattersi): Likewise. (*avx512f_scatterdi): Likewise. (*andnot3_bcst): Fix VI/VI48_AVX512VL typo. From-SVN: r273161 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 262244db0d09..1b318b9f7c96 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2019-07-06 Richard Sandiford + + * config/i386/i386.md (*fop__3_i387) + (l2): Fix ambiguous uses + of .md attributes. + * config/i386/sse.md (*avx512pf_gatherpfsf_mask) + (*avx512pf_gatherpfdf_mask, *avx512pf_scatterpfsf_mask) + (*avx512pf_scatterpfdf_mask, *avx2_gathersi) + (*avx2_gathersi_2, *avx2_gatherdi) + (*avx2_gatherdi_2, *avx2_gatherdi_3): Likewise. + (*avx2_gatherdi_4, *avx512f_gathersi): Likewise. + (*avx512f_gathersi_2, *avx512f_gatherdi): Likewise. + (*avx512f_gatherdi_2, *avx512f_scattersi): Likewise. + (*avx512f_scatterdi): Likewise. + (*andnot3_bcst): Fix VI/VI48_AVX512VL typo. + 2019-07-06 Richard Sandiford * config/h8300/h8300.md (*push1_h8300hs_): Explicitly diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c401deb5eb00..db5fa9ae3cae 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14755,7 +14755,7 @@ ] (const_string "fop"))) (set_attr "fp_int_src" "true") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_insn "*fop_xf_4_i387" [(set (match_operand:XF 0 "register_operand" "=f,f") @@ -16457,7 +16457,7 @@ { rtx tmp = gen_reg_rtx (mode); - emit_insn (gen_sse4_1_round2 + emit_insn (gen_sse4_1_round2 (tmp, operands[1], GEN_INT (ROUND_ | ROUND_NO_EXC))); emit_insn (gen_fix_trunc2 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3fa45609005a..3ce22395c653 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12702,8 +12702,8 @@ (const_string "")))]) (define_insn "*andnot3_bcst" - [(set (match_operand:VI 0 "register_operand" "=v") - (and:VI + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (and:VI48_AVX512VL (not:VI48_AVX512VL (match_operand:VI48_AVX512VL 1 "register_operand" "v")) (vec_duplicate:VI48_AVX512VL @@ -18084,7 +18084,7 @@ operands[3]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512pf_gatherpfsf_mask" +(define_insn "*avx512pf_gatherpfsf_mask" [(unspec [(match_operand: 0 "register_operand" "Yk") (match_operator: 5 "vsib_mem_operator" @@ -18131,7 +18131,7 @@ operands[3]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512pf_gatherpfdf_mask" +(define_insn "*avx512pf_gatherpfdf_mask" [(unspec [(match_operand: 0 "register_operand" "Yk") (match_operator:V8DF 5 "vsib_mem_operator" @@ -18178,7 +18178,7 @@ operands[3]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512pf_scatterpfsf_mask" +(define_insn "*avx512pf_scatterpfsf_mask" [(unspec [(match_operand: 0 "register_operand" "Yk") (match_operator: 5 "vsib_mem_operator" @@ -18227,7 +18227,7 @@ operands[3]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512pf_scatterpfdf_mask" +(define_insn "*avx512pf_scatterpfdf_mask" [(unspec [(match_operand: 0 "register_operand" "Yk") (match_operator:V8DF 5 "vsib_mem_operator" @@ -21016,7 +21016,7 @@ operands[5]), UNSPEC_VSIBADDR); }) -(define_insn "*avx2_gathersi" +(define_insn "*avx2_gathersi" [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") (unspec:VEC_GATHER_MODE [(match_operand:VEC_GATHER_MODE 2 "register_operand" "0") @@ -21036,7 +21036,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "*avx2_gathersi_2" +(define_insn "*avx2_gathersi_2" [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") (unspec:VEC_GATHER_MODE [(pc) @@ -21077,7 +21077,7 @@ operands[5]), UNSPEC_VSIBADDR); }) -(define_insn "*avx2_gatherdi" +(define_insn "*avx2_gatherdi" [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") (unspec:VEC_GATHER_MODE [(match_operand: 2 "register_operand" "0") @@ -21097,7 +21097,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "*avx2_gatherdi_2" +(define_insn "*avx2_gatherdi_2" [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") (unspec:VEC_GATHER_MODE [(pc) @@ -21113,7 +21113,7 @@ (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] "TARGET_AVX2" { - if (mode != mode) + if (mode != mode) return "%M2vgatherq\t{%4, %6, %x0|%x0, %6, %4}"; return "%M2vgatherq\t{%4, %6, %0|%0, %6, %4}"; } @@ -21121,7 +21121,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "*avx2_gatherdi_3" +(define_insn "*avx2_gatherdi_3" [(set (match_operand: 0 "register_operand" "=&x") (vec_select: (unspec:VI4F_256 @@ -21144,7 +21144,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "*avx2_gatherdi_4" +(define_insn "*avx2_gatherdi_4" [(set (match_operand: 0 "register_operand" "=&x") (vec_select: (unspec:VI4F_256 @@ -21186,7 +21186,7 @@ operands[5]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512f_gathersi" +(define_insn "*avx512f_gathersi" [(set (match_operand:VI48F 0 "register_operand" "=&v") (unspec:VI48F [(match_operand:VI48F 1 "register_operand" "0") @@ -21207,7 +21207,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "*avx512f_gathersi_2" +(define_insn "*avx512f_gathersi_2" [(set (match_operand:VI48F 0 "register_operand" "=&v") (unspec:VI48F [(pc) @@ -21248,7 +21248,7 @@ operands[5]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512f_gatherdi" +(define_insn "*avx512f_gatherdi" [(set (match_operand:VI48F 0 "register_operand" "=&v") (unspec:VI48F [(match_operand: 1 "register_operand" "0") @@ -21269,7 +21269,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "*avx512f_gatherdi_2" +(define_insn "*avx512f_gatherdi_2" [(set (match_operand:VI48F 0 "register_operand" "=&v") (unspec:VI48F [(pc) @@ -21286,9 +21286,9 @@ { /* %X5 so that we don't emit any *WORD PTR for -masm=intel, as gas changed what it requires incompatibly. */ - if (mode != mode) + if (mode != mode) { - if ( != 64) + if ( != 64) return "%M3vgatherq\t{%5, %x0%{%1%}|%x0%{%1%}, %X5}"; else return "%M3vgatherq\t{%5, %t0%{%1%}|%t0%{%1%}, %X5}"; @@ -21317,7 +21317,7 @@ operands[4]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512f_scattersi" +(define_insn "*avx512f_scattersi" [(set (match_operator:VI48F 5 "vsib_mem_operator" [(unspec:P [(match_operand:P 0 "vsib_address_operand" "Tv") @@ -21355,7 +21355,7 @@ operands[4]), UNSPEC_VSIBADDR); }) -(define_insn "*avx512f_scatterdi" +(define_insn "*avx512f_scatterdi" [(set (match_operator:VI48F 5 "vsib_mem_operator" [(unspec:P [(match_operand:P 0 "vsib_address_operand" "Tv")