From: Stephen Boyd Date: Wed, 26 Feb 2025 22:33:45 +0000 (-0800) Subject: Merge tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel... X-Git-Tag: v6.15-rc1~103^2~2^2~1 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a0e2025fda0617de339003c7aef8349bfd6558c9;p=thirdparty%2Fkernel%2Flinux.git Merge tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add thermal (TSU) clock, reset, and power domain on Renesas RZ/G3S - Add AI accelerator (DRP-AI) clocks and reset on Renesas RZ/V2L - Add Image Signal Processor (ISP, FCPVX, VSPX) clocks on Renesas R-Car V3U V4H, and V4M - Add Watchdog (WDT), SDHI, Interrupt Controller (ICU), Camera (CRU0) and CAN-FD clocks and resets on Renesas RZ/G3E * tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g047: Add CANFD clocks and resets clk: renesas: r9a09g047: Add CRU0 clocks and resets clk: renesas: rzv2h: Update error message clk: renesas: rzg2l: Update error message clk: renesas: r9a09g047: Add ICU clock/reset clk: renesas: r9a07g043: Fix HP clock source for RZ/Five clk: renesas: r9a09g047: Add SDHI clocks/resets clk: renesas: r8a779h0: Add VSPX clock clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a08g045: Check the source of the CPU PLL settings clk: renesas: r9a09g047: Add WDT clocks and resets clk: renesas: r8a779h0: Add ISP core clocks clk: renesas: r8a779g0: Add ISP core clocks clk: renesas: r8a779a0: Add ISP core clocks clk: renesas: r8a779a0: Add FCPVX clocks clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validation --- a0e2025fda0617de339003c7aef8349bfd6558c9