From: Petar Jovanovic <mips32r2@gmail.com>
Date: Tue, 22 Aug 2017 14:05:00 +0000 (+0200)
Subject: mips: remove incorrect implementation of several Iops
X-Git-Tag: VALGRIND_3_14_0~279
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a1e5547a44db46bab055b8907f129e5679b1d36a;p=thirdparty%2Fvalgrind.git

mips: remove incorrect implementation of several Iops

Remove incorrect implementation of
  Iop_DivModU64to32
  Iop_DivModS64to32
  Iop_DivModU128to64
  Iop_DivModS128to64
---

diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index 2c49a6eb70..deb33f2b4d 100644
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -1188,36 +1188,6 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
             return r_ccIR;
          }
 
-         if (e->Iex.Binop.op == Iop_DivModU64to32 ||
-             e->Iex.Binop.op == Iop_DivModS64to32) {
-            HReg tLo = newVRegI(env);
-            HReg tHi = newVRegI(env);
-            HReg mask = newVRegI(env);
-            HReg tLo_1 = newVRegI(env);
-            HReg tHi_1 = newVRegI(env);
-            HReg r_dst = newVRegI(env);
-            Bool syned = toBool(e->Iex.Binop.op == Iop_DivModS64to32);
-
-            HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
-            HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
-
-            addInstr(env, MIPSInstr_Div(syned, True, r_srcL, r_srcR));
-            addInstr(env, MIPSInstr_Mfhi(tHi));
-            addInstr(env, MIPSInstr_Mflo(tLo));
-
-            addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tHi_1, tHi,
-                                         MIPSRH_Imm(False, 32)));
-
-            addInstr(env, MIPSInstr_LI(mask, 0xffffffff));
-            addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
-                          MIPSRH_Reg(mask)));
-
-            addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
-                          MIPSRH_Reg(tLo_1)));
-
-            return r_dst;
-         }
-
          if (e->Iex.Binop.op == Iop_DivModU32to32 ||
              e->Iex.Binop.op == Iop_DivModS32to32) {
             HReg tLo = newVRegI(env);
@@ -2262,25 +2232,6 @@ static void iselInt128Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env,
             return;
          }
 
-         case Iop_DivModU128to64:
-         case Iop_DivModS128to64: {
-            vassert(mode64);
-            HReg rHi1, rLo1;
-            iselInt128Expr(&rHi1, &rLo1, env, e->Iex.Binop.arg1);
-
-            HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
-            HReg tLo = newVRegI(env);
-            HReg tHi = newVRegI(env);
-            Bool syned = toBool(e->Iex.Binop.op == Iop_DivModS128to64);
-
-            addInstr(env, MIPSInstr_Div(syned, False, rLo1, r_srcR));
-            addInstr(env, MIPSInstr_Mfhi(tHi));
-            addInstr(env, MIPSInstr_Mflo(tLo));
-            *rHi = tHi;
-            *rLo = tLo;
-            return;
-         }
-
          default:
             break;
       }
@@ -2475,23 +2426,6 @@ static void iselInt64Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
 
             return;
          }
-         case Iop_DivModS64to32:
-         case Iop_DivModU64to32: {
-            HReg r_sHi, r_sLo;
-            HReg tLo = newVRegI(env);
-            HReg tHi = newVRegI(env);
-            Bool syned = toBool(op_binop == Iop_DivModS64to32);
-            HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
-
-            iselInt64Expr(&r_sHi, &r_sLo, env, e->Iex.Binop.arg1);
-            addInstr(env, MIPSInstr_Div(syned, True, r_sLo, r_srcR));
-            addInstr(env, MIPSInstr_Mfhi(tHi));
-            addInstr(env, MIPSInstr_Mflo(tLo));
-            *rHi = tHi;
-            *rLo = tLo;
-
-            return;
-         }
 
          case Iop_DivModU32to32:
          case Iop_DivModS32to32: {
diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index 946e93249e..7f9ce90b03 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -144,12 +144,12 @@ static irop_t irops[] = {
   { DEFOP(Iop_DivS32E,    UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
   // On s390 the DivMod operations always appear in a certain context
   // So they cannot be tested in isolation on that platform.
-  { DEFOP(Iop_DivModU64to32,  UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
-  { DEFOP(Iop_DivModS64to32,  UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+  { DEFOP(Iop_DivModU64to32,  UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+  { DEFOP(Iop_DivModS64to32,  UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
   { DEFOP(Iop_DivModU32to32,  UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
   { DEFOP(Iop_DivModS32to32,  UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
-  { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
-  { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
+  { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
+  { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
   { DEFOP(Iop_DivModS64to64,  UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
   { DEFOP(Iop_DivModU64to64,  UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
   { DEFOP(Iop_8Uto16,    UNDEF_ZEXT),   .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },