From: Christoph Müllner <christoph.muellner@vrull.eu>
Date: Tue, 25 Apr 2023 13:24:13 +0000 (+0200)
Subject: riscv: Define Xmode macro
X-Git-Tag: basepoints/gcc-15~7686
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a3480aacc4ab01651725a63e05829a43bc23d549;p=thirdparty%2Fgcc.git

riscv: Define Xmode macro

Define a Xmode macro that specifies the registers size (XLEN)
similar to Pmode. This allows the backend code to write generic
RV32/RV64 C code (under certain circumstances).

gcc/ChangeLog:

	* config/riscv/riscv.h (Xmode): New macro.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 83dcac165b51..7d548ac4b23b 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -800,6 +800,10 @@ typedef struct {
 
 #define Pmode word_mode
 
+/* Specify the machine mode that registers have.  */
+
+#define Xmode (TARGET_64BIT ? DImode : SImode)
+
 /* Give call MEMs SImode since it is the "most permissive" mode
    for both 32-bit and 64-bit targets.  */