From: Uros Bizjak Date: Mon, 14 May 2012 21:32:29 +0000 (+0200) Subject: re PR target/46098 (ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store... X-Git-Tag: releases/gcc-4.6.4~546 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a4c339355225189368d37382d9136923a81ad12c;p=thirdparty%2Fgcc.git re PR target/46098 (ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()) PR target/46098 * config/i386/i386.c (ix86_expand_special_args_builtin): Always generate target register for "load" class builtins. Revert: 2010-10-22 Uros Bizjak PR target/46098 * config/i386/sse.md (*avx_movu): Rename from avx_movu. (avx_movu): New expander. (*_movu): Rename from _movu. (_movu): New expander. (*avx_movdqu): Rename from avx_movdqu. (avx_movdqu): New expander. (*sse2_movdqu): Rename from sse2_movdqu. (sse2_movdqu): New expander. testsuite/ChangeLog: * gcc.target/i386/avx256-unaligned-load-[1234].c: Update scan strings. * gcc.target/i386/avx256-unaligned-store-[1234].c: Ditto. From-SVN: r187483 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b97a5dea3be3..4563e0aa44ba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2012-05-14 Uros Bizjak + + PR target/46098 + * config/i386/i386.c (ix86_expand_special_args_builtin): Always + generate target register for "load" class builtins. + + Revert: + 2010-10-22 Uros Bizjak + + PR target/46098 + * config/i386/sse.md (*avx_movu): + Rename from avx_movu. + (avx_movu): New expander. + (*_movu): Rename from _movu. + (_movu): New expander. + (*avx_movdqu): Rename from avx_movdqu. + (avx_movdqu): New expander. + (*sse2_movdqu): Rename from sse2_movdqu. + (sse2_movdqu): New expander. + 2012-05-13 Uros Bizjak Backport from mainline diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 8c27488ebf93..9e2d66cd9cac 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -27230,8 +27230,8 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, arg_adjust = 0; if (optimize || target == 0 - || GET_MODE (target) != tmode - || !insn_p->operand[0].predicate (target, tmode)) + || !register_operand (target, tmode) + || GET_MODE (target) != tmode) target = gen_reg_rtx (tmode); } diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ba997c22436d..b0dc3d8db808 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -392,18 +392,7 @@ DONE; }) -(define_expand "avx_movu" - [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "") - (unspec:AVXMODEF2P - [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")] - UNSPEC_MOVU))] - "AVX_VEC_FLOAT_MODE_P (mode)" -{ - if (MEM_P (operands[0]) && MEM_P (operands[1])) - operands[1] = force_reg (mode, operands[1]); -}) - -(define_insn "*avx_movu" +(define_insn "avx_movu" [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m") (unspec:AVXMODEF2P [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")] @@ -429,18 +418,7 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) -(define_expand "_movu" - [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "") - (unspec:SSEMODEF2P - [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")] - UNSPEC_MOVU))] - "SSE_VEC_FLOAT_MODE_P (mode)" -{ - if (MEM_P (operands[0]) && MEM_P (operands[1])) - operands[1] = force_reg (mode, operands[1]); -}) - -(define_insn "*_movu" +(define_insn "_movu" [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m") (unspec:SSEMODEF2P [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")] @@ -452,18 +430,7 @@ (set_attr "movu" "1") (set_attr "mode" "")]) -(define_expand "avx_movdqu" - [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "") - (unspec:AVXMODEQI - [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")] - UNSPEC_MOVU))] - "TARGET_AVX" -{ - if (MEM_P (operands[0]) && MEM_P (operands[1])) - operands[1] = force_reg (mode, operands[1]); -}) - -(define_insn "*avx_movdqu" +(define_insn "avx_movdqu" [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m") (unspec:AVXMODEQI [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")] @@ -475,17 +442,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_expand "sse2_movdqu" - [(set (match_operand:V16QI 0 "nonimmediate_operand" "") - (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")] - UNSPEC_MOVU))] - "TARGET_SSE2" -{ - if (MEM_P (operands[0]) && MEM_P (operands[1])) - operands[1] = force_reg (V16QImode, operands[1]); -}) - -(define_insn "*sse2_movdqu" +(define_insn "sse2_movdqu" [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m") (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")] UNSPEC_MOVU))] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 984a01134c33..327205980e6a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2012-05-14 Uros Bizjak + + * gcc.target/i386/avx256-unaligned-load-[1234].c: Update scan strings. + * gcc.target/i386/avx256-unaligned-store-[1234].c: Ditto. + 2012-05-03 Michael Meissner Backport from mainline diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c index 023e859b6c1d..c1c7517d7113 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "\\*avx_movups256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movups/1" } } */ +/* { dg-final { scan-assembler-not "avx_movups256/1" } } */ +/* { dg-final { scan-assembler "avx_movups/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c index 8394e27197b2..319cf5e0a018 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "\\*avx_movdqu256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movdqu/1" } } */ +/* { dg-final { scan-assembler-not "avx_movdqu256/1" } } */ +/* { dg-final { scan-assembler "avx_movdqu/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c index ec7d59d53cce..6ac579aa77c9 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "\\*avx_movupd256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movupd/1" } } */ +/* { dg-final { scan-assembler-not "avx_movupd256/1" } } */ +/* { dg-final { scan-assembler "avx_movupd/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c index 0d3ef3331206..7c015a8b90a7 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c @@ -14,6 +14,6 @@ avx_test (void) b[i] = a[i+3] * 2; } -/* { dg-final { scan-assembler "\\*avx_movups256/1" } } */ -/* { dg-final { scan-assembler-not "\\*avx_movups/1" } } */ +/* { dg-final { scan-assembler "avx_movups256/1" } } */ +/* { dg-final { scan-assembler-not "avx_movups/1" } } */ /* { dg-final { scan-assembler-not "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c index 99db55c9d0ad..cf1944acab2c 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "\\*avx_movups256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movups256/2" } } */ /* { dg-final { scan-assembler "movups.*\\*avx_movv4sf_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c index 38ee9e2a45c5..5a10ec3a7fba 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "\\*avx_movdqu256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movdqu256/2" } } */ /* { dg-final { scan-assembler "movdqu.*\\*avx_movv16qi_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c index eaab6fd775b9..daea7b0ea813 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "\\*avx_movupd256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movupd256/2" } } */ /* { dg-final { scan-assembler "movupd.*\\*avx_movv2df_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c index 96cca66ae9c7..39b6f3bef169 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c @@ -14,7 +14,7 @@ avx_test (void) b[i+3] = a[i] * c[i]; } -/* { dg-final { scan-assembler "\\*avx_movups256/2" } } */ -/* { dg-final { scan-assembler-not "\\*avx_movups/2" } } */ +/* { dg-final { scan-assembler "avx_movups256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movups/2" } } */ /* { dg-final { scan-assembler-not "\\*avx_movv4sf_internal/3" } } */ /* { dg-final { scan-assembler-not "vextractf128" } } */