From: Charles Baylis Date: Fri, 17 Jan 2014 11:57:02 +0000 (+0000) Subject: backport: re PR target/59142 (internal compiler error while compiling OpenCV 2.4.7) X-Git-Tag: releases/gcc-4.7.4~311 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a4e6860aca1bb4f76f813cc773d2755d60ae535c;p=thirdparty%2Fgcc.git backport: re PR target/59142 (internal compiler error while compiling OpenCV 2.4.7) 2014-01-17 Charles Baylis Backport from mainline 2013-12-19 Charles Baylis PR target/59142 * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb patterns. * config/arm/ldmstm.md: Regenerate. 2013-12-19 Charles Baylis PR target/59142 * config/arm/predicates.md (arm_hard_general_register_operand): New predicate. (arm_hard_register_operand): Remove. * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand for all patterns. * config/arm/ldmstm.md: Regenerate. From-SVN: r206707 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b52ea8b58dea..21fe4d7bb483 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2014-01-17 Charles Baylis + + Backport from mainline + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb + patterns. + * config/arm/ldmstm.md: Regenerate. + + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/predicates.md (arm_hard_general_register_operand): + New predicate. + (arm_hard_register_operand): Remove. + * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand + for all patterns. + * config/arm/ldmstm.md: Regenerate. + 2014-01-16 Jakub Jelinek PR target/59839 diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml index 221edd2aa31a..97264c073852 100644 --- a/gcc/config/arm/arm-ldmstm.ml +++ b/gcc/config/arm/arm-ldmstm.ml @@ -67,10 +67,13 @@ let destreg nregs first op_type thumb = Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") (nregs + 1) (inout_constr op_type) (constr thumb) +let reg_predicate thumb = + if thumb then "low_register_operand" else "arm_hard_general_register_operand" + let write_ldm_set thumb nregs offset opnr first = let indent = " " in Printf.printf "%s" (if first then " [" else indent); - Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; + Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb); Printf.printf "%s (mem:SI " indent; begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); @@ -84,7 +87,7 @@ let write_stm_set thumb nregs offset opnr first = begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); begin if offset != 0 then Printf.printf " (const_int %d))" offset end; - Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr + Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb) let write_ldm_peep_set extra_indent nregs opnr first = let indent = " " ^ extra_indent in diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md index 5db4a3269968..b9be43e9156a 100644 --- a/gcc/config/arm/ldmstm.md +++ b/gcc/config/arm/ldmstm.md @@ -23,15 +23,15 @@ (define_insn "*ldm4_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -41,15 +41,15 @@ (define_insn "*thumb_ldm4_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" @@ -60,15 +60,15 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" @@ -80,15 +80,15 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 5))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" @@ -98,13 +98,13 @@ (define_insn "*stm4_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -115,13 +115,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -132,29 +132,29 @@ [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4")]) (define_insn "*ldm4_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" @@ -166,16 +166,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" @@ -186,13 +186,13 @@ (define_insn "*stm4_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -203,13 +203,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(ib%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -217,16 +217,16 @@ (define_insn "*ldm4_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%5, {%1, %2, %3, %4}" @@ -237,16 +237,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "ldm%(da%)\t%5!, {%1, %2, %3, %4}" @@ -256,13 +256,13 @@ (define_insn "*stm4_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -273,13 +273,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(da%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -287,16 +287,16 @@ (define_insn "*ldm4_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -308,16 +308,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -16)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" @@ -328,13 +328,13 @@ (define_insn "*stm4_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -345,13 +345,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(db%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -466,12 +466,12 @@ (define_insn "*ldm3_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -481,12 +481,12 @@ (define_insn "*thumb_ldm3_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" @@ -497,12 +497,12 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -514,12 +514,12 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 4))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" @@ -529,11 +529,11 @@ (define_insn "*stm3_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -544,11 +544,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -559,24 +559,24 @@ [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3")]) (define_insn "*ldm3_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" @@ -588,13 +588,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" @@ -605,11 +605,11 @@ (define_insn "*stm3_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -620,11 +620,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -632,13 +632,13 @@ (define_insn "*ldm3_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%4, {%1, %2, %3}" @@ -649,13 +649,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%4!, {%1, %2, %3}" @@ -665,11 +665,11 @@ (define_insn "*stm3_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -680,11 +680,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -692,13 +692,13 @@ (define_insn "*ldm3_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -710,13 +710,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -727,11 +727,11 @@ (define_insn "*stm3_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -742,11 +742,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -847,9 +847,9 @@ (define_insn "*ldm2_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" @@ -859,9 +859,9 @@ (define_insn "*thumb_ldm2_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" @@ -872,9 +872,9 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -886,9 +886,9 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 3))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" @@ -898,9 +898,9 @@ (define_insn "*stm2_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(ia%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -911,9 +911,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -924,19 +924,19 @@ [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2")]) (define_insn "*ldm2_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" @@ -948,10 +948,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" @@ -962,9 +962,9 @@ (define_insn "*stm2_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(ib%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -975,9 +975,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -985,10 +985,10 @@ (define_insn "*ldm2_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "ldm%(da%)\t%3, {%1, %2}" @@ -999,10 +999,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%3!, {%1, %2}" @@ -1012,9 +1012,9 @@ (define_insn "*stm2_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(da%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -1025,9 +1025,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -1035,10 +1035,10 @@ (define_insn "*ldm2_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" @@ -1050,10 +1050,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -1064,9 +1064,9 @@ (define_insn "*stm2_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(db%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -1077,9 +1077,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%3!, {%1, %2}" [(set_attr "type" "store2") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index fa2f695356be..e8d00cbe79be 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -31,11 +31,11 @@ || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); }) -;; Any hard register. -(define_predicate "arm_hard_register_operand" +;; Any general register. +(define_predicate "arm_hard_general_register_operand" (match_code "reg") { - return REGNO (op) < FIRST_PSEUDO_REGISTER; + return REGNO (op) <= LAST_ARM_REGNUM; }) ;; A low register.