From: Peter Bergner Date: Tue, 23 Jan 2018 18:18:25 +0000 (-0600) Subject: backport: re PR target/83399 (Power8 ICE During LRA with 2-op rtl pattern for lvx... X-Git-Tag: releases/gcc-6.5.0~565 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a5014b7479293a0a8d451f90fa63251f8bdd7c61;p=thirdparty%2Fgcc.git backport: re PR target/83399 (Power8 ICE During LRA with 2-op rtl pattern for lvx instruction) gcc/ Back port from mainline 2018-01-10 Peter Bergner PR target/83399 * config/rs6000/rs6000.c (print_operand) <'y'>: Use VECTOR_MEM_ALTIVEC_OR_VSX_P. * config/rs6000/vsx.md (*vsx_le_perm_load_ for VSX_D): Use indexed_or_indirect_operand predicate. (*vsx_le_perm_load_ for VSX_W): Likewise. (*vsx_le_perm_load_v8hi): Likewise. (*vsx_le_perm_load_v16qi): Likewise. (*vsx_le_perm_store_ for VSX_D): Likewise. (*vsx_le_perm_store_ for VSX_W): Likewise. (*vsx_le_perm_store_v8hi): Likewise. (*vsx_le_perm_store_v16qi): Likewise. (eight unnamed splitters): Likewise. gcc/testsuite/ Back port from mainline 2018-01-10 Peter Bergner PR target/83399 * gcc.target/powerpc/pr83399.c: New test. From-SVN: r256993 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aa3d31fa128d..8d92bd8f4b70 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2018-01-23 Peter Bergner + + Back port from mainline + 2018-01-10 Peter Bergner + + PR target/83399 + * config/rs6000/rs6000.c (print_operand) <'y'>: Use + VECTOR_MEM_ALTIVEC_OR_VSX_P. + * config/rs6000/vsx.md (*vsx_le_perm_load_ for VSX_D): Use + indexed_or_indirect_operand predicate. + (*vsx_le_perm_load_ for VSX_W): Likewise. + (*vsx_le_perm_load_v8hi): Likewise. + (*vsx_le_perm_load_v16qi): Likewise. + (*vsx_le_perm_store_ for VSX_D): Likewise. + (*vsx_le_perm_store_ for VSX_W): Likewise. + (*vsx_le_perm_store_v8hi): Likewise. + (*vsx_le_perm_store_v16qi): Likewise. + (eight unnamed splitters): Likewise. + 2018-01-23 Michael Meissner Back port from trunk diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c5754f6e3c6b..6423bf38da1f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -21342,7 +21342,7 @@ print_operand (FILE *file, rtx x, int code) /* Fall through. Must be [reg+reg]. */ } - if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x)) + if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x)) && GET_CODE (tmp) == AND && GET_CODE (XEXP (tmp, 1)) == CONST_INT && INTVAL (XEXP (tmp, 1)) == -16) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d0715e951e62..ca8a702a7b96 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -298,7 +298,7 @@ ;; VSX moves so they match first. (define_insn_and_split "*vsx_le_perm_load_" [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") - (match_operand:VSX_D 1 "memory_operand" "Z"))] + (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -321,7 +321,7 @@ (define_insn_and_split "*vsx_le_perm_load_" [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") - (match_operand:VSX_W 1 "memory_operand" "Z"))] + (match_operand:VSX_W 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -346,7 +346,7 @@ (define_insn_and_split "*vsx_le_perm_load_v8hi" [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") - (match_operand:V8HI 1 "memory_operand" "Z"))] + (match_operand:V8HI 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -375,7 +375,7 @@ (define_insn_and_split "*vsx_le_perm_load_v16qi" [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (match_operand:V16QI 1 "memory_operand" "Z"))] + (match_operand:V16QI 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -411,7 +411,7 @@ (set_attr "length" "8")]) (define_insn "*vsx_le_perm_store_" - [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "=Z") (match_operand:VSX_D 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -419,7 +419,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_D 0 "memory_operand" "") + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "") (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -438,7 +438,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_D 0 "memory_operand" "") + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "") (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) @@ -456,7 +456,7 @@ "") (define_insn "*vsx_le_perm_store_" - [(set (match_operand:VSX_W 0 "memory_operand" "=Z") + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z") (match_operand:VSX_W 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -464,7 +464,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_W 0 "memory_operand" "") + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "") (match_operand:VSX_W 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -485,7 +485,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_W 0 "memory_operand" "") + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "") (match_operand:VSX_W 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) @@ -506,7 +506,7 @@ "") (define_insn "*vsx_le_perm_store_v8hi" - [(set (match_operand:V8HI 0 "memory_operand" "=Z") + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "=Z") (match_operand:V8HI 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -514,7 +514,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:V8HI 0 "memory_operand" "") + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "") (match_operand:V8HI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -539,7 +539,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:V8HI 0 "memory_operand" "") + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "") (match_operand:V8HI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) @@ -566,7 +566,7 @@ "") (define_insn "*vsx_le_perm_store_v16qi" - [(set (match_operand:V16QI 0 "memory_operand" "=Z") + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "=Z") (match_operand:V16QI 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -574,7 +574,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:V16QI 0 "memory_operand" "") + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "") (match_operand:V16QI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -607,7 +607,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:V16QI 0 "memory_operand" "") + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "") (match_operand:V16QI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e141ba6e78d3..6da5bf16f237 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2018-01-23 Peter Bergner + + Back port from mainline + 2018-01-10 Peter Bergner + + PR target/83399 + * gcc.target/powerpc/pr83399.c: New test. + 2018-01-23 Michael Meissner Back port from trunk diff --git a/gcc/testsuite/gcc.target/powerpc/pr83399.c b/gcc/testsuite/gcc.target/powerpc/pr83399.c new file mode 100644 index 000000000000..96d9b3821842 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr83399.c @@ -0,0 +1,15 @@ +/* PR target/83399 */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O1 -mabi=elfv2 -mlittle -mvsx" } */ + +typedef __attribute__((altivec(vector__))) int v4si_t; +int +foo (void) +{ + v4si_t a, u, v, y; + u = __builtin_altivec_lvx (32, ((void *) &a) - 32); + v = __builtin_altivec_lvx (64, ((void *) &a) - 32); + y = u + v; + return y[0]; +}