From: H. Peter Anvin Date: Wed, 22 Feb 2012 01:25:50 +0000 (-0800) Subject: x86, cpufeature: Add CPU features from Intel document 319433-012A X-Git-Tag: v3.2.98~42 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a55c7b6ed442564e3793e20420cf7fdf96ae9ebf;p=thirdparty%2Fkernel%2Fstable.git x86, cpufeature: Add CPU features from Intel document 319433-012A commit 513c4ec6e4759aa33c90af0658b82eb4d2027871 upstream. Add CPU features from the Intel Archicture Instruction Set Extensions Programming Reference version 012A (Feb 2012), document number 319433-012A. Signed-off-by: H. Peter Anvin Signed-off-by: Hugh Dickins Signed-off-by: Ben Hutchings --- diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index b8a5fe545f95a..6f254f2fcd40d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -198,8 +198,11 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ #define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ +#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ +#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ +#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ #if defined(__KERNEL__) && !defined(__ASSEMBLY__)