From: Christoph Müllner <christoph.muellner@vrull.eu>
Date: Tue, 7 Apr 2026 19:22:35 +0000 (+0200)
Subject: riscv: add hwprobe-based CI entries for capability detection
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a6130eb4c195db47dc43df8c7b7e76b99a9cb907;p=thirdparty%2Fopenssl.git

riscv: add hwprobe-based CI entries for capability detection

All existing RISC-V cross-compile matrix entries set OPENSSL_riscvcap,
which causes OPENSSL_cpuid_setup() to call parse_env() and skip the
hwprobe_to_cap() code path entirely.  That path has never been exercised
by CI, leaving bugs in it undetectable.

Add two matrix entries that omit opensslcapsname so OPENSSL_riscvcap is
not set and hwprobe_to_cap() is called:

- rv64gc_novector_hwprobe: rv64 with ZBB/ZBC/ZBS/ZBKB, V disabled.
  AT_HWCAP V bit is clear (VECTOR_CAPABLE=false).  Exercises the
  scalar-extension detection branch of hwprobe_to_cap().

- rv64gc_v_zvkned_hwprobe: rv64 with V (vlen=128) and ZVKNED.
  AT_HWCAP V bit is set (VECTOR_CAPABLE=true).  Exercises the
  vector-extension detection branch and the IS_IN_DEPEND_VECTOR
  guard that gates Zvk* extensions on V availability.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Reviewed-by: Eugene Syromiatnikov <esyr@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.foundation>
MergeDate: Thu Apr 16 17:03:41 2026
(Merged from https://github.com/openssl/openssl/pull/30713)
---

diff --git a/.github/workflows/riscv-more-cross-compiles.yml b/.github/workflows/riscv-more-cross-compiles.yml
index 42f295943f6..2c86b75e4be 100644
--- a/.github/workflows/riscv-more-cross-compiles.yml
+++ b/.github/workflows/riscv-more-cross-compiles.yml
@@ -202,6 +202,29 @@ jobs:
             qemucpu: "rv64,zbb=true,zbkb=true,zknh=true,zksh=true",
             opensslcapsname: riscvcap, # OPENSSL_riscvcap
             opensslcaps: "rv64gc_inlineasm" # for uploading artifact
+          }, {
+            # hwprobe path: RV64GC without V, no OPENSSL_riscvcap override.
+            # Forces the hwprobe_to_cap() code path (skipped when OPENSSL_riscvcap is set).
+            # V is absent so AT_HWCAP V bit is clear (VECTOR_CAPABLE=false).
+            # The rv64 CPU model includes ZBB/ZBC/ZBS/ZBKB by default.
+            arch: riscv64-linux-gnu,
+            libs: libc6-dev-riscv64-cross,
+            target: linux64-riscv64,
+            fips: no,
+            qemucpu: "rv64,zbb=true,zbc=true,zbs=true,zbkb=true,v=false",
+            # No opensslcapsname: hwprobe is used for capability detection.
+            opensslcaps: "rv64gc_novector_hwprobe",
+          }, {
+            # hwprobe path: RV64GC + V + ZVKNED (vlen=128), no OPENSSL_riscvcap override.
+            # Forces the hwprobe_to_cap() code path (skipped when OPENSSL_riscvcap is set).
+            # V is present so AT_HWCAP V bit is set (VECTOR_CAPABLE=true).
+            arch: riscv64-linux-gnu,
+            libs: libc6-dev-riscv64-cross,
+            target: linux64-riscv64,
+            fips: no,
+            qemucpu: "rv64,v=true,vlen=128,zvkned=true",
+            # No opensslcapsname: hwprobe is used for capability detection.
+            opensslcaps: "rv64gc_v_zvkned_hwprobe",
           }
         ]
     runs-on: ubuntu-latest