From: Patrick O'Neill <patrick@rivosinc.com>
Date: Wed, 5 Apr 2023 16:47:05 +0000 (-0700)
Subject: RISC-V: Add AMO release bits
X-Git-Tag: basepoints/gcc-15~9737
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a61a067b15221de981afd4df8433e96a8cf32341;p=thirdparty%2Fgcc.git

RISC-V: Add AMO release bits

This patch sets the relevant .rl bits on amo operations.

2023-04-27 Patrick O'Neill <patrick@rivosinc.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_print_operand): Change behavior
	of %A to include release bits.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 11af780fc3ee..f8bc402e35a8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4508,8 +4508,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       break;
 
     case 'A':
-      if (riscv_memmodel_needs_amo_acquire (model))
+      if (riscv_memmodel_needs_amo_acquire (model)
+	  && riscv_memmodel_needs_release_fence (model))
+	fputs (".aqrl", file);
+      else if (riscv_memmodel_needs_amo_acquire (model))
 	fputs (".aq", file);
+      else if (riscv_memmodel_needs_release_fence (model))
+	fputs (".rl", file);
       break;
 
     case 'F':