From: Philippe Mathieu-Daudé Date: Thu, 29 Jan 2026 15:03:24 +0000 (+0100) Subject: disas: Have disas_set_info() take a const CPUState X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a63b90ca6ce8d00dee5150b84bbc65428519ef2b;p=thirdparty%2Fqemu.git disas: Have disas_set_info() take a const CPUState The CPUClass::disas_set_info() handler is meant to initialize the %disassemble_info structure; it shoudn't alter the CPU state. Enforce the CPUState can not be modified by having the handler take a const pointer. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-ID: <20260202222412.24923-8-philmd@linaro.org> --- diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 98678704a6..ef20cb356a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -175,7 +175,7 @@ struct CPUClass { const char * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_core_xml_file)(CPUState *cpu); - void (*disas_set_info)(CPUState *cpu, disassemble_info *info); + void (*disas_set_info)(const CPUState *cpu, disassemble_info *info); const char *deprecation_note; struct AccelCPUClass *accel_cpu; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 932cddac05..1780db7d1e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -98,7 +98,8 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) return alpha_env_mmu_index(cpu_env(cs)); } -static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void alpha_cpu_disas_set_info(const CPUState *cpu, + disassemble_info *info) { info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_mach_alpha_ev6; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 586202071d..c535b292d9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -789,10 +789,10 @@ static void arm_wfxt_timer_cb(void *opaque) } #endif -static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) +static void arm_disas_set_info(const CPUState *cpu, disassemble_info *info) { - ARMCPU *ac = ARM_CPU(cpu); - CPUARMState *env = &ac->env; + const ARMCPU *ac = ARM_CPU(cpu); + const CPUARMState *env = &ac->env; bool sctlr_b = arm_sctlr_b(env); if (is_a64(env)) { diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 52237da3ce..8579a7283b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -116,7 +116,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType type) memset(env->r, 0, sizeof(env->r)); } -static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void avr_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info) { info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_arch_avr; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 8ac4f49aa3..58a22ee41f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -301,7 +301,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) set_float_default_nan_pattern(0b11111111, &env->fp_status); } -static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void hexagon_cpu_disas_set_info(const CPUState *cs, + disassemble_info *info) { info->print_insn = print_insn_hexagon; info->endian = BFD_ENDIAN_LITTLE; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 0ca79ee5e2..714f3bbdaf 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -150,7 +150,7 @@ static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; } -static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) +static void hppa_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) { info->mach = bfd_mach_hppa20; info->endian = BFD_ENDIAN_BIG; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 45f0b80deb..0a7b884528 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10359,10 +10359,10 @@ static bool x86_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static void x86_disas_set_info(CPUState *cs, disassemble_info *info) +static void x86_disas_set_info(const CPUState *cs, disassemble_info *info) { - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; + const X86CPU *cpu = X86_CPU(cs); + const CPUX86State *env = &cpu->env; info->endian = BFD_ENDIAN_LITTLE; info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b653948526..4fa629cb14 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -506,7 +506,8 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) cs->exception_index = -1; } -static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void loongarch_cpu_disas_set_info(const CPUState *cs, + disassemble_info *info) { info->endian = BFD_ENDIAN_LITTLE; info->print_insn = print_insn_loongarch; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b55e604b11..c721a23b96 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -176,7 +176,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) env->pc = 0; } -static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void m68k_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) { info->print_insn = print_insn_m68k; info->endian = BFD_ENDIAN_BIG; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 53649ec656..ae41a1a328 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -233,7 +233,7 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) #endif } -static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) +static void mb_disas_set_info(const CPUState *cpu, disassemble_info *info) { info->mach = bfd_arch_microblaze; info->print_insn = print_insn_microblaze; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f74a9d5f61..e424d11501 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -422,9 +422,12 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) #endif } -static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) { - if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { + const MIPSCPU *cpu = MIPS_CPU(cs); + const CPUMIPSState *env = &cpu->env; + + if (!(env->insn_flags & ISA_NANOMIPS32)) { info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 9bbfe22ed3..c64542a59a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -94,7 +94,7 @@ static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) return MMU_NOMMU_IDX; /* mmu is disabled */ } -static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) +static void openrisc_disas_set_info(const CPUState *cpu, disassemble_info *info) { info->endian = BFD_ENDIAN_BIG; info->print_insn = print_insn_or1k; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c5cec7c2ed..c36fd118a9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7452,9 +7452,10 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) return pcc->pvr == pvr; } -static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) +static void ppc_disas_set_info(const CPUState *cs, disassemble_info *info) { - CPUPPCState *env = cpu_env(cs); + const PowerPCCPU *cpu = POWERPC_CPU(cs); + const CPUPPCState *env = &cpu->env; info->endian = ppc_env_is_little_endian(env) ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e95eea0249..e56470a374 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -795,10 +795,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) #endif } -static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *info) { - RISCVCPU *cpu = RISCV_CPU(s); - CPURISCVState *env = &cpu->env; + const RISCVCPU *cpu = RISCV_CPU(s); + const CPURISCVState *env = &cpu->env; + info->target_info = &cpu->cfg; /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 0437edca1b..b5284199e6 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -178,7 +178,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int request) } } -static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void rx_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info) { info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_mach_rx; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index cd472d38be..c074e12ba2 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -222,7 +222,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) } } -static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void s390_cpu_disas_set_info(const CPUState *cpu, disassemble_info *info) { info->mach = bfd_mach_s390_64; info->cap_arch = CS_ARCH_SYSZ; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1dd21ad9ed..e2bde45761 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -164,7 +164,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); } -static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void superh_cpu_disas_set_info(const CPUState *cpu, + disassemble_info *info) { info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bfc6fb9d00..3991681d1d 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -103,7 +103,8 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } #endif /* !CONFIG_USER_ONLY */ -static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) +static void cpu_sparc_disas_set_info(const CPUState *cpu, + disassemble_info *info) { info->print_insn = print_insn_sparc; info->endian = BFD_ENDIAN_BIG; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ecc5e093a4..86ec899a67 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -226,7 +226,8 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) return oc; } -static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) +static void xtensa_cpu_disas_set_info(const CPUState *cs, + disassemble_info *info) { XtensaCPU *cpu = XTENSA_CPU(cs);