From: Edwin Lu <ewlu@rivosinc.com>
Date: Wed, 15 Nov 2023 21:22:11 +0000 (-0800)
Subject: RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]
X-Git-Tag: basepoints/gcc-15~4599
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a671095c208c7cf5eb934b6a31bd9fb6f6640a6b;p=thirdparty%2Fgcc.git

RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]

Fix __riscv_unaligned_fast/slow/avoid macro name to
__riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec

	PR target/111557

gcc/ChangeLog:

	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/attribute-1.c: update macro name
	* gcc.target/riscv/attribute-4.c: ditto
	* gcc.target/riscv/attribute-5.c: ditto
	* gcc.target/riscv/predef-align-1.c: ditto
	* gcc.target/riscv/predef-align-2.c: ditto
	* gcc.target/riscv/predef-align-3.c: ditto
	* gcc.target/riscv/predef-align-4.c: ditto
	* gcc.target/riscv/predef-align-5.c: ditto
	* gcc.target/riscv/predef-align-6.c: ditto

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index b7f9ba204f7f..dd1bd0596fc2 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -109,11 +109,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
     }
 
   if (riscv_user_wants_strict_align)
-    builtin_define_with_int_value ("__riscv_unaligned_avoid", 1);
+    builtin_define_with_int_value ("__riscv_misaligned_avoid", 1);
   else if (riscv_slow_unaligned_access_p)
-    builtin_define_with_int_value ("__riscv_unaligned_slow", 1);
+    builtin_define_with_int_value ("__riscv_misaligned_slow", 1);
   else
-    builtin_define_with_int_value ("__riscv_unaligned_fast", 1);
+    builtin_define_with_int_value ("__riscv_misaligned_fast", 1);
 
   if (TARGET_MIN_VLEN != 0)
     builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite/gcc.target/riscv/attribute-1.c
index abfb0b498e0c..a39efb3e6ff3 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-1.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c
@@ -4,13 +4,13 @@ int foo()
 {
 
 /* In absence of -m[no-]strict-align, default mcpu is currently 
-   set to rocket.  rocket has slow_unaligned_access=true.  */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+   set to rocket.  rocket has slow_misaligned_access=true.  */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set"
 #endif
 
 return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite/gcc.target/riscv/attribute-4.c
index 545f87cb8992..a5a95042a314 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-4.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c
@@ -3,12 +3,12 @@
 int foo()
 {
 
-#if !defined(__riscv_unaligned_avoid)
-#error "__riscv_unaligned_avoid is not set"
+#if !defined(__riscv_misaligned_avoid)
+#error "__riscv_misaligned_avoid is not set"
 #endif
 
-#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite/gcc.target/riscv/attribute-5.c
index 753043c31e93..ad1a1811fa35 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-5.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c
@@ -3,13 +3,13 @@
 int foo()
 {
 
-/* Default mcpu is rocket which has slow_unaligned_access=true.  */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+/* Default mcpu is rocket which has slow_misaligned_access=true.  */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set"
 #endif
 
 return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-1.c b/gcc/testsuite/gcc.target/riscv/predef-align-1.c
index 9dde37a721ec..fb8c5f74035b 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-align-1.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-1.c
@@ -3,13 +3,13 @@
 
 int main() {
 
-/* thead-c906 default is cpu tune param unaligned access fast */
-#if !defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_fast is not set"
+/* thead-c906 default is cpu tune param misaligned access fast */
+#if !defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_fast is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpectedly set"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-2.c b/gcc/testsuite/gcc.target/riscv/predef-align-2.c
index 33d604f5aa0b..50ab67e04f5d 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-align-2.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-2.c
@@ -3,12 +3,12 @@
 
 int main() {
 
-#if !defined(__riscv_unaligned_avoid)
-#error "__riscv_unaligned_avoid is not set"
+#if !defined(__riscv_misaligned_avoid)
+#error "__riscv_misaligned_avoid is not set"
 #endif
 
-#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-3.c b/gcc/testsuite/gcc.target/riscv/predef-align-3.c
index daf5718a39fb..5c586907cb0f 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-align-3.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-3.c
@@ -3,13 +3,13 @@
 
 int main() {
 
-/* thead-c906 default is cpu tune param unaligned access fast */
-#if !defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_fast is not set"
+/* thead-c906 default is cpu tune param misaligned access fast */
+#if !defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_fast is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpectedly set"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-4.c b/gcc/testsuite/gcc.target/riscv/predef-align-4.c
index d46a46f252d1..6fbdc7f7d414 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-align-4.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-4.c
@@ -3,13 +3,13 @@
 
 int main() {
 
-/* rocket default is cpu tune param unaligned access slow */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+/* rocket default is cpu tune param misaligned access slow */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-5.c b/gcc/testsuite/gcc.target/riscv/predef-align-5.c
index 3aa25f8e0e00..4a40081d86d8 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-align-5.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-5.c
@@ -3,12 +3,12 @@
 
 int main() {
 
-#if !defined(__riscv_unaligned_avoid)
-#error "__riscv_unaligned_avoid is not set"
+#if !defined(__riscv_misaligned_avoid)
+#error "__riscv_misaligned_avoid is not set"
 #endif
 
-#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-6.c b/gcc/testsuite/gcc.target/riscv/predef-align-6.c
index cb64d7e77789..18eb72cfc602 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-align-6.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-6.c
@@ -3,13 +3,13 @@
 
 int main() {
 
-/* rocket default is cpu tune param unaligned access slow */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+/* rocket default is cpu tune param misaligned access slow */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set"
 #endif
 
   return 0;