From: Zoltan HERPAI Date: Sat, 3 May 2025 22:29:54 +0000 (+0200) Subject: kernel/d1: Restore kernel files for v6.6 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a68467f307dd3d5eeafc811adcc25661e9cfbcf5;p=thirdparty%2Fopenwrt.git kernel/d1: Restore kernel files for v6.6 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Zoltan HERPAI --- diff --git a/target/linux/d1/config-6.6 b/target/linux/d1/config-6.6 new file mode 100644 index 00000000000..0bfcdf79585 --- /dev/null +++ b/target/linux/d1/config-6.6 @@ -0,0 +1,414 @@ +CONFIG_64BIT=y +# CONFIG_ACPI is not set +# CONFIG_AHCI_SUNXI is not set +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUNXI=y +# CONFIG_ARCH_THEAD is not set +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +# CONFIG_AX45MP_L2_CACHE is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_COMPAT_BRK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DMADEVICES=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_SUN6I=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_SUN8I=y +CONFIG_DWMAC_SUNXI=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EFI=y +CONFIG_EFIVAR_FS=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +# CONFIG_EFI_ZBOOT is not set +CONFIG_ELF_CORE=y +# CONFIG_ERRATA_ANDES is not set +# CONFIG_ERRATA_SIFIVE is not set +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_PBMT=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_FAILOVER=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FPU=y +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_PCF857X=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OCORES=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_STACKS=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_LEDS_PWM_MULTICOLOR is not set +# CONFIG_LEDS_SUN50I_A100 is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_SUN4I is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_AXP20X=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_SUN4I_GPADC is not set +CONFIG_MFD_SUN6I_PRCM=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SUNXI=y +CONFIG_MMIOWB=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_NLS=y +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_USB_XCEIV=y +CONFIG_NR_CPUS=8 +CONFIG_NVMEM=y +CONFIG_NVMEM_SUNXI_SID=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DMA_DEFAULT_COHERENT=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OID_REGISTRY=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PGTABLE_LEVELS=5 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN50I_USB3=y +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +CONFIG_PORTABLE=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_SIFIVE is not set +# CONFIG_PWM_SUN4I is not set +# CONFIG_PWM_SUN8I_V536 is not set +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_XILINX is not set +CONFIG_RATIONAL=y +CONFIG_RCU_TRACE=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_AXP20X is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_SUN20I=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_BOOT_SPINWAIT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_V01=y +CONFIG_RISCV_TIMER=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_DEBUG=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +# CONFIG_SND_SUN20I_CODEC is not set +# CONFIG_SND_SUN20I_D1_CODEC_ANALOG is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN50I_DMIC is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +# CONFIG_SOC_SIFIVE is not set +# CONFIG_SOC_STARFIVE is not set +# CONFIG_SOC_VIRT is not set +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_SUN4I is not set +CONFIG_SPI_SUN6I=y +CONFIG_SRCU=y +CONFIG_STACKDEPOT=y +CONFIG_STACKTRACE=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +CONFIG_SUN20I_GPADC=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +CONFIG_SUN50I_IOMMU=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_R_CCU is not set +CONFIG_SUN8I_THERMAL=y +CONFIG_SUNXI_CCU=y +# CONFIG_SUNXI_RSB is not set +CONFIG_SUNXI_SRAM=y +CONFIG_SUNXI_WATCHDOG=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THREAD_SIZE_ORDER=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOOLCHAIN_HAS_ZICBOM=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +CONFIG_TRACE_CLOCK=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TUNE_GENERIC=y +# CONFIG_UACCE is not set +CONFIG_UCS2_STRING=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_HID=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_VHOST_MENU is not set +# CONFIG_VIRTIO_MENU is not set +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch b/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch new file mode 100644 index 00000000000..4652b640fe7 --- /dev/null +++ b/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch @@ -0,0 +1,64 @@ +From c6fd43b8420f3864ad1cd64d818d9b9abc2cb711 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 28 Aug 2023 12:30:22 +0800 +Subject: [PATCH 01/14] riscv: dts: allwinner: d1: Add PMU event node + +D1 has several pmu events supported by opensbi. +These events can be used by perf for profiling. + +Signed-off-by: Inochi Amaoto +Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf +Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 +Acked-by: Conor Dooley +Acked-by: Jernej Skrabec +Reviewed-by: Guo Ren +--- + arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +@@ -72,4 +72,43 @@ + #interrupt-cells = <2>; + }; + }; ++ ++ pmu { ++ compatible = "riscv,pmu"; ++ riscv,event-to-mhpmcounters = ++ <0x00003 0x00003 0x00000008>, ++ <0x00004 0x00004 0x00000010>, ++ <0x00005 0x00005 0x00000200>, ++ <0x00006 0x00006 0x00000100>, ++ <0x10000 0x10000 0x00004000>, ++ <0x10001 0x10001 0x00008000>, ++ <0x10002 0x10002 0x00010000>, ++ <0x10003 0x10003 0x00020000>, ++ <0x10019 0x10019 0x00000040>, ++ <0x10021 0x10021 0x00000020>; ++ riscv,event-to-mhpmevent = ++ <0x00003 0x00000000 0x00000001>, ++ <0x00004 0x00000000 0x00000002>, ++ <0x00005 0x00000000 0x00000007>, ++ <0x00006 0x00000000 0x00000006>, ++ <0x10000 0x00000000 0x0000000c>, ++ <0x10001 0x00000000 0x0000000d>, ++ <0x10002 0x00000000 0x0000000e>, ++ <0x10003 0x00000000 0x0000000f>, ++ <0x10019 0x00000000 0x00000004>, ++ <0x10021 0x00000000 0x00000003>; ++ riscv,raw-event-to-mhpmcounters = ++ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, ++ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, ++ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, ++ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, ++ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, ++ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, ++ <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, ++ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, ++ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, ++ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, ++ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, ++ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; ++ }; + }; diff --git a/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch b/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch new file mode 100644 index 00000000000..db3ce3dcca6 --- /dev/null +++ b/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch @@ -0,0 +1,59 @@ +From 99942611816c117a01f16dbcab54908a49b378c3 Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:39 +0100 +Subject: [PATCH 02/14] riscv: dts: allwinner: Update opp table to allow CPU + frequency scaling + +Two OPPs are currently defined for the D1/D1s; one at 408MHz and +another at 1.08GHz. Switching between these can be done with the +"sun50i-cpufreq-nvmem" driver. This patch populates the opp table +appropriately, inspired by +https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi + +The supply voltages are PWM-controlled, but support for that IP +is still in the works. So stick to a target vdd-cpu supply of 0.9V, +which seems to be the default on most D1 boards. + +Signed-off-by: Brandon Cheo Fusi +--- + arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +@@ -36,16 +36,22 @@ + }; + + opp_table_cpu: opp-table-cpu { +- compatible = "operating-points-v2"; ++ compatible = "allwinner,sun20i-d1-operating-points", ++ "allwinner,sun50i-h6-operating-points"; ++ nvmem-cells = <&cpu_speed_grade>; ++ nvmem-cell-names = "speed"; ++ opp-shared; + + opp-408000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <900000 900000 1100000>; ++ opp-microvolt-speed0 = <900000 900000 1100000>; + }; + + opp-1080000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <900000 900000 1100000>; ++ opp-microvolt-speed0 = <900000 900000 1100000>; + }; + }; + +@@ -112,3 +118,9 @@ + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; + }; + }; ++ ++&sid { ++ cpu_speed_grade: cpu-speed-grade@0 { ++ reg = <0x00 0x2>; ++ }; ++}; diff --git a/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch b/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch new file mode 100644 index 00000000000..b60551be86c --- /dev/null +++ b/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch @@ -0,0 +1,25 @@ +From e904f32e5fe694ed7b8d1cd914bcf2bfd67e896c Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:40 +0100 +Subject: [PATCH 03/14] dt-bindings: opp: sun50i: Add binding for D1 CPUs + +Add binding for D1 CPU OPPs. + +Signed-off-by: Brandon Cheo Fusi +--- + .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml ++++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml +@@ -23,7 +23,9 @@ allOf: + + properties: + compatible: +- const: allwinner,sun50i-h6-operating-points ++ enum: ++ - allwinner,sun50i-h6-operating-points ++ - allwinner,sun20i-d1-operating-points + + nvmem-cells: + description: | diff --git a/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch b/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch new file mode 100644 index 00000000000..e918156eb13 --- /dev/null +++ b/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch @@ -0,0 +1,23 @@ +From b294def636629cc4d9feff4ed610a0d0c68a58fd Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:41 +0100 +Subject: [PATCH 04/14] cpufreq: sun50i: Add D1 support + +Add support for D1 based devices to the Allwinner H6 cpufreq +driver + +Signed-off-by: Brandon Cheo Fusi +--- + drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c ++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c +@@ -160,6 +160,7 @@ static struct platform_driver sun50i_cpu + + static const struct of_device_id sun50i_cpufreq_match_list[] = { + { .compatible = "allwinner,sun50i-h6" }, ++ { .compatible = "allwinner,sun20i-d1" }, + {} + }; + MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list); diff --git a/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch b/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch new file mode 100644 index 00000000000..3127a0e9bbc --- /dev/null +++ b/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch @@ -0,0 +1,23 @@ +From 9d78aafd278577ef2a9d92127c9d35b00989c057 Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:42 +0100 +Subject: [PATCH 05/14] cpufreq: dt-platdev: Blocklist allwinner,sun20i-d1 SoC + +The Allwinner D1 uses H6 cpufreq driver. Add it to blocklist +so the "cpufreq-dt" device is not created twice. + +Signed-off-by: Brandon Cheo Fusi +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -104,6 +104,7 @@ static const struct of_device_id allowli + */ + static const struct of_device_id blocklist[] __initconst = { + { .compatible = "allwinner,sun50i-h6", }, ++ { .compatible = "allwinner,sun20i-d1", }, + + { .compatible = "apple,arm-platform", }, + diff --git a/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch b/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch new file mode 100644 index 00000000000..7ff3095ebc1 --- /dev/null +++ b/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch @@ -0,0 +1,69 @@ +From e4a8ff817e133d84f8a82f78461e0592e5e9d9cc Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:43 +0100 +Subject: [PATCH 06/14] cpufreq: Make sun50i h6 cpufreq Kconfig option arch + generic + +Move the Allwinner SUN50I cpufreq driver from Kconfig.arm to the +main Kconfig file so it supports other architectures, like RISC-V +in our case, and drop the 'ARM_' prefix. + +Signed-off-by: Brandon Cheo Fusi +--- + drivers/cpufreq/Kconfig | 12 ++++++++++++ + drivers/cpufreq/Kconfig.arm | 12 ------------ + drivers/cpufreq/Makefile | 2 +- + 3 files changed, 13 insertions(+), 13 deletions(-) + +--- a/drivers/cpufreq/Kconfig ++++ b/drivers/cpufreq/Kconfig +@@ -312,5 +312,17 @@ config QORIQ_CPUFREQ + This adds the CPUFreq driver support for Freescale QorIQ SoCs + which are capable of changing the CPU's frequency dynamically. + ++config ALLWINNER_SUN50I_CPUFREQ_NVMEM ++ tristate "Allwinner nvmem based SUN50I CPUFreq driver" ++ depends on ARCH_SUNXI ++ depends on NVMEM_SUNXI_SID ++ select PM_OPP ++ help ++ This adds the nvmem based CPUFreq driver for Allwinner ++ h6/D1 SoCs. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called sun50i-cpufreq-nvmem. ++ + endif + endmenu +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -29,18 +29,6 @@ config ACPI_CPPC_CPUFREQ_FIE + + If in doubt, say N. + +-config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM +- tristate "Allwinner nvmem based SUN50I CPUFreq driver" +- depends on ARCH_SUNXI +- depends on NVMEM_SUNXI_SID +- select PM_OPP +- help +- This adds the nvmem based CPUFreq driver for Allwinner +- h6 SoC. +- +- To compile this driver as a module, choose M here: the +- module will be called sun50i-cpufreq-nvmem. +- + config ARM_APPLE_SOC_CPUFREQ + tristate "Apple Silicon SoC CPUFreq support" + depends on ARCH_APPLE || (COMPILE_TEST && 64BIT) +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -78,7 +78,7 @@ obj-$(CONFIG_ARM_SCMI_CPUFREQ) += scmi- + obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o + obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o + obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o +-obj-$(CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o ++obj-$(CONFIG_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o + obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o + obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o + obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o diff --git a/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch b/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch new file mode 100644 index 00000000000..ad50d9130cb --- /dev/null +++ b/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch @@ -0,0 +1,116 @@ +From 3341f884d75929a009801d4299d219e64c64a33c Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:01 +0300 +Subject: [PATCH 07/14] ASoC: dt-bindings: sun4i-a10-codec: Add binding for + Allwinner D1 SoC + +The Allwinner D1 SoC has a internal audio codec that similar to previous +ones, but it contains a three ADC channels instead of two, and also has +a separate clocks for ADC and DAC modules. + +Signed-off-by: Maksim Kiselev +Reviewed-by: Rob Herring +--- + .../sound/allwinner,sun4i-a10-codec.yaml | 64 ++++++++++++++++--- + 1 file changed, 56 insertions(+), 8 deletions(-) + +--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml ++++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml +@@ -22,6 +22,7 @@ properties: + - allwinner,sun8i-a23-codec + - allwinner,sun8i-h3-codec + - allwinner,sun8i-v3s-codec ++ - allwinner,sun20i-d1-codec + + reg: + maxItems: 1 +@@ -29,15 +30,9 @@ properties: + interrupts: + maxItems: 1 + +- clocks: +- items: +- - description: Bus Clock +- - description: Module Clock ++ clocks: true + +- clock-names: +- items: +- - const: apb +- - const: codec ++ clock-names: true + + dmas: + items: +@@ -106,11 +101,42 @@ allOf: + - if: + properties: + compatible: ++ const: allwinner,sun20i-d1-codec ++ then: ++ properties: ++ clocks: ++ items: ++ - description: Bus Clock ++ - description: ADC Module Clock ++ - description: DAC Module Clock ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: adc ++ - const: dac ++ ++ else: ++ properties: ++ clocks: ++ items: ++ - description: Bus Clock ++ - description: Module Clock ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: codec ++ ++ - if: ++ properties: ++ compatible: + enum: + - allwinner,sun6i-a31-codec + - allwinner,sun8i-a23-codec + - allwinner,sun8i-h3-codec + - allwinner,sun8i-v3s-codec ++ - allwinner,sun20i-d1-codec + + then: + if: +@@ -225,6 +251,28 @@ allOf: + - Headphone + - Headset Mic + - Line In ++ - Line Out ++ - Mic ++ - Speaker ++ ++ - if: ++ properties: ++ compatible: ++ enum: ++ - allwinner,sun20i-d1-codec ++ ++ then: ++ properties: ++ allwinner,audio-routing: ++ items: ++ enum: ++ - HP ++ - LINEIN ++ - MIC3 ++ - MBIAS ++ - Headphone ++ - Headset Mic ++ - Line In + - Line Out + - Mic + - Speaker diff --git a/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch b/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch new file mode 100644 index 00000000000..d25a27de925 --- /dev/null +++ b/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch @@ -0,0 +1,51 @@ +From 64efc9cc704d27c60dc9c96a02d842f22dbdfeae Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:02 +0300 +Subject: [PATCH 08/14] ASoC: dt-bindings: Add schema for + "allwinner,sun20i-d1-codec-analog" + +Add a DT schema to describe the analog part of the Allwinner D1/T113s +internal audio codec. + +Signed-off-by: Maksim Kiselev +--- + .../allwinner,sun20i-d1-codec-analog.yaml | 33 +++++++++++++++++++ + 1 file changed, 33 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml +@@ -0,0 +1,33 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/allwinner,sun20i-d1-codec-analog.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Allwinner D1 Analog Codec ++ ++maintainers: ++ - Maksim Kiselev ++ ++properties: ++ compatible: ++ const: allwinner,sun20i-d1-codec-analog ++ ++ reg: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ ++additionalProperties: false ++ ++examples: ++ - | ++ codec_analog: codec-analog@2030300 { ++ compatible = "allwinner,sun20i-d1-codec-analog"; ++ reg = <0x02030300 0xd00>; ++ }; ++ ++... ++ diff --git a/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch b/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch new file mode 100644 index 00000000000..242f8f7a0e4 --- /dev/null +++ b/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch @@ -0,0 +1,614 @@ +From 0963766bc665769aebf370d44ee3a97facfbca57 Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:03 +0300 +Subject: [PATCH 09/14] ASoC: sunxi: sun4i-codec: add basic support for D1 + audio codec + +Allwinner D1 has an audio codec similar to earlier ones, but it comes +with 3 channel ADC instead of 2, and many registers are moved. + +Add basic support for it. + +Signed-off-by: Maksim Kiselev +--- + sound/soc/sunxi/sun4i-codec.c | 364 ++++++++++++++++++++++++++++------ + 1 file changed, 300 insertions(+), 64 deletions(-) + +--- a/sound/soc/sunxi/sun4i-codec.c ++++ b/sound/soc/sunxi/sun4i-codec.c +@@ -232,15 +232,65 @@ + + /* TODO H3 DAP (Digital Audio Processing) bits */ + ++/* ++ * sun20i D1 and similar codecs specific registers ++ * ++ * Almost all registers moved on D1, including ADC digital controls, ++ * FIFO and RX data registers. Only DAC control are at the same offset. ++ */ ++ ++#define SUN20I_D1_CODEC_DAC_VOL_CTRL (0x04) ++#define SUN20I_D1_CODEC_DAC_VOL_SEL (16) ++#define SUN20I_D1_CODEC_DAC_VOL_L (8) ++#define SUN20I_D1_CODEC_DAC_VOL_R (0) ++#define SUN20I_D1_CODEC_DAC_FIFOC (0x10) ++#define SUN20I_D1_CODEC_ADC_FIFOC (0x30) ++#define SUN20I_D1_CODEC_ADC_FIFOC_EN_AD (28) ++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (16) ++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (4) ++#define SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN (3) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1 (0x34) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL (16) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL (8) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL (0) ++#define SUN20I_D1_CODEC_ADC_RXDATA (0x40) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL (0x50) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN (2) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN (1) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN (0) ++#define SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL (0x54) ++ ++/* TODO D1 DAP (Digital Audio Processing) bits */ ++ ++struct sun4i_codec; ++ ++struct sun4i_codec_quirks { ++ const struct regmap_config *regmap_config; ++ const struct snd_soc_component_driver *codec; ++ struct snd_soc_card * (*create_card)(struct device *dev); ++ struct reg_field reg_dac_fifoc; /* used for regmap_field */ ++ struct reg_field reg_adc_fifoc; /* used for regmap_field */ ++ unsigned int adc_drq_en; ++ unsigned int rx_sample_bits; ++ unsigned int rx_trig_level; ++ unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ ++ unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ ++ bool has_reset; ++ bool has_dual_clock; ++}; ++ + struct sun4i_codec { + struct device *dev; + struct regmap *regmap; + struct clk *clk_apb; +- struct clk *clk_module; ++ struct clk *clk_module; /* used for ADC if clocks are separate */ ++ struct clk *clk_module_dac; + struct reset_control *rst; + struct gpio_desc *gpio_pa; ++ const struct sun4i_codec_quirks *quirks; + +- /* ADC_FIFOC register is at different offset on different SoCs */ ++ /* DAC/ADC FIFOC registers are at different offset on different SoCs */ ++ struct regmap_field *reg_dac_fifoc; + struct regmap_field *reg_adc_fifoc; + + struct snd_dmaengine_dai_dma_data capture_dma_data; +@@ -250,33 +300,33 @@ struct sun4i_codec { + static void sun4i_codec_start_playback(struct sun4i_codec *scodec) + { + /* Flush TX FIFO */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); + + /* Enable DAC DRQ */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); + } + + static void sun4i_codec_stop_playback(struct sun4i_codec *scodec) + { + /* Disable DAC DRQ */ +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); + } + + static void sun4i_codec_start_capture(struct sun4i_codec *scodec) + { + /* Enable ADC DRQ */ + regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN)); ++ BIT(scodec->quirks->adc_drq_en)); + } + + static void sun4i_codec_stop_capture(struct sun4i_codec *scodec) + { + /* Disable ADC DRQ */ + regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN)); ++ BIT(scodec->quirks->adc_drq_en)); + } + + static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd, +@@ -325,8 +375,8 @@ static int sun4i_codec_prepare_capture(s + + /* Set RX FIFO trigger level */ + regmap_field_update_bits(scodec->reg_adc_fifoc, +- 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, +- 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL); ++ 0xf << scodec->quirks->rx_trig_level, ++ 0x7 << scodec->quirks->rx_trig_level); + + /* + * FIXME: Undocumented in the datasheet, but +@@ -360,13 +410,13 @@ static int sun4i_codec_prepare_playback( + u32 val; + + /* Flush the TX FIFO */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); + + /* Set TX FIFO Empty Trigger Level */ +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL, +- 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL, ++ 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL); + + if (substream->runtime->rate > 32000) + /* Use 64 bits FIR filter */ +@@ -375,13 +425,12 @@ static int sun4i_codec_prepare_playback( + /* Use 32 bits FIR filter */ + val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION); + +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), +- val); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), val); + + /* Send zeros when we have an underrun */ +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT)); + + return 0; + }; +@@ -476,30 +525,32 @@ static int sun4i_codec_hw_params_capture + 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS, + hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS); + +- /* Set the number of channels we want to use */ +- if (params_channels(params) == 1) +- regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); +- else +- regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); ++ if (!scodec->quirks->has_dual_clock) { ++ /* Set the number of channels we want to use */ ++ if (params_channels(params) == 1) ++ regmap_field_set_bits(scodec->reg_adc_fifoc, ++ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); ++ else ++ regmap_field_clear_bits(scodec->reg_adc_fifoc, ++ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); ++ } + + /* Set the number of sample bits to either 16 or 24 bits */ + if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { + regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS)); ++ BIT(scodec->quirks->rx_sample_bits)); + + regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); ++ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); + + scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + } else { + regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS)); ++ BIT(scodec->quirks->rx_sample_bits)); + + /* Fill most significant bits with valid data MSB */ + regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); ++ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); + + scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + } +@@ -514,9 +565,9 @@ static int sun4i_codec_hw_params_playbac + u32 val; + + /* Set DAC sample rate */ +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS, +- hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS, ++ hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS); + + /* Set the number of channels we want to use */ + if (params_channels(params) == 1) +@@ -524,27 +575,26 @@ static int sun4i_codec_hw_params_playbac + else + val = 0; + +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), +- val); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), val); + + /* Set the number of sample bits to either 16 or 24 bits */ + if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); + + /* Set TX FIFO mode to padding the LSBs with 0 */ +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); + + scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + } else { +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); + + /* Set TX FIFO mode to repeat the MSB */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); + + scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + } +@@ -565,7 +615,11 @@ static int sun4i_codec_hw_params(struct + if (!clk_freq) + return -EINVAL; + +- ret = clk_set_rate(scodec->clk_module, clk_freq); ++ if (scodec->clk_module_dac && ++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ ret = clk_set_rate(scodec->clk_module_dac, clk_freq); ++ else ++ ret = clk_set_rate(scodec->clk_module, clk_freq); + if (ret) + return ret; + +@@ -607,10 +661,14 @@ static int sun4i_codec_startup(struct sn + * Stop issuing DRQ when we have room for less than 16 samples + * in our TX FIFO + */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT); + +- return clk_prepare_enable(scodec->clk_module); ++ if (scodec->clk_module_dac && ++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ return clk_prepare_enable(scodec->clk_module_dac); ++ else ++ return clk_prepare_enable(scodec->clk_module); + } + + static void sun4i_codec_shutdown(struct snd_pcm_substream *substream, +@@ -619,7 +677,11 @@ static void sun4i_codec_shutdown(struct + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); + +- clk_disable_unprepare(scodec->clk_module); ++ if (scodec->clk_module_dac && ++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ clk_disable_unprepare(scodec->clk_module_dac); ++ else ++ clk_disable_unprepare(scodec->clk_module); + } + + static const struct snd_soc_dai_ops sun4i_codec_dai_ops = { +@@ -1229,6 +1291,55 @@ static const struct snd_soc_component_dr + .endianness = 1, + }; + ++/* sun20i D1 codec */ ++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_dvol_scale, -12000, 75, 1); ++ ++static const struct snd_kcontrol_new sun20i_d1_codec_codec_controls[] = { ++ SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC, ++ SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1, ++ sun6i_codec_dvol_scale), ++ SOC_DOUBLE_TLV("DAC Front Playback Volume", SUN20I_D1_CODEC_DAC_VOL_CTRL, ++ SUN20I_D1_CODEC_DAC_VOL_L, SUN20I_D1_CODEC_DAC_VOL_R, ++ 0xFF, 0, sun20i_d1_codec_dvol_scale), ++ ++ SOC_SINGLE_TLV("ADC1 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1, ++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL, 0xff, 0, ++ sun20i_d1_codec_dvol_scale), ++ SOC_SINGLE_TLV("ADC2 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1, ++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL, 0xff, 0, ++ sun20i_d1_codec_dvol_scale), ++ SOC_SINGLE_TLV("ADC3 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1, ++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL, 0xff, 0, ++ sun20i_d1_codec_dvol_scale), ++}; ++ ++static const struct snd_soc_dapm_widget sun20i_d1_codec_codec_widgets[] = { ++ /* Digital parts of the ADCs */ ++ SND_SOC_DAPM_SUPPLY("ADC Enable", SUN20I_D1_CODEC_ADC_FIFOC, ++ SUN20I_D1_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("ADC1 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL, ++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("ADC2 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL, ++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("ADC3 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL, ++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN, 0, NULL, 0), ++ /* Digital parts of the DACs */ ++ SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC, ++ SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("DAC VOL_SEL Enable", SUN20I_D1_CODEC_DAC_VOL_CTRL, ++ SUN20I_D1_CODEC_DAC_VOL_SEL, 0, NULL, 0), ++}; ++ ++static const struct snd_soc_component_driver sun20i_d1_codec_codec = { ++ .controls = sun20i_d1_codec_codec_controls, ++ .num_controls = ARRAY_SIZE(sun20i_d1_codec_codec_controls), ++ .dapm_widgets = sun20i_d1_codec_codec_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(sun20i_d1_codec_codec_widgets), ++ .idle_bias_on = 1, ++ .use_pmdown_time = 1, ++ .endianness = 1, ++}; ++ + static const struct snd_soc_component_driver sun4i_codec_component = { + .name = "sun4i-codec", + .legacy_dai_naming = 1, +@@ -1532,6 +1643,66 @@ static struct snd_soc_card *sun8i_v3s_co + return card; + }; + ++static const struct snd_soc_dapm_route sun20i_d1_codec_card_routes[] = { ++ /* ADC Routes */ ++ { "ADC1", NULL, "ADC Enable" }, ++ { "ADC2", NULL, "ADC Enable" }, ++ { "ADC3", NULL, "ADC Enable" }, ++ { "ADC1", NULL, "ADC1 CH Enable" }, ++ { "ADC2", NULL, "ADC2 CH Enable" }, ++ { "ADC3", NULL, "ADC3 CH Enable" }, ++ { "Codec Capture", NULL, "ADC1" }, ++ { "Codec Capture", NULL, "ADC2" }, ++ { "Codec Capture", NULL, "ADC3" }, ++ ++ /* DAC Routes */ ++ { "Left DAC", NULL, "DAC Enable" }, ++ { "Right DAC", NULL, "DAC Enable" }, ++ { "Left DAC", NULL, "DAC VOL_SEL Enable" }, ++ { "Right DAC", NULL, "DAC VOL_SEL Enable" }, ++ { "Left DAC", NULL, "Codec Playback" }, ++ { "Right DAC", NULL, "Codec Playback" }, ++}; ++ ++static struct snd_soc_card *sun20i_d1_codec_create_card(struct device *dev) ++{ ++ struct snd_soc_card *card; ++ int ret; ++ ++ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); ++ if (!card) ++ return ERR_PTR(-ENOMEM); ++ ++ aux_dev.dlc.of_node = of_parse_phandle(dev->of_node, ++ "allwinner,codec-analog-controls", ++ 0); ++ if (!aux_dev.dlc.of_node) { ++ dev_err(dev, "Can't find analog controls for codec.\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ card->dai_link = sun4i_codec_create_link(dev, &card->num_links); ++ if (!card->dai_link) ++ return ERR_PTR(-ENOMEM); ++ ++ card->dev = dev; ++ card->owner = THIS_MODULE; ++ card->name = "D1 Audio Codec"; ++ card->dapm_widgets = sun6i_codec_card_dapm_widgets; ++ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); ++ card->dapm_routes = sun20i_d1_codec_card_routes; ++ card->num_dapm_routes = ARRAY_SIZE(sun20i_d1_codec_card_routes); ++ card->aux_dev = &aux_dev; ++ card->num_aux_devs = 1; ++ card->fully_routed = true; ++ ++ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); ++ if (ret) ++ dev_warn(dev, "failed to parse audio-routing: %d\n", ret); ++ ++ return card; ++}; ++ + static const struct regmap_config sun4i_codec_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -1574,21 +1745,22 @@ static const struct regmap_config sun8i_ + .max_register = SUN8I_H3_CODEC_ADC_DBG, + }; + +-struct sun4i_codec_quirks { +- const struct regmap_config *regmap_config; +- const struct snd_soc_component_driver *codec; +- struct snd_soc_card * (*create_card)(struct device *dev); +- struct reg_field reg_adc_fifoc; /* used for regmap_field */ +- unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ +- unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ +- bool has_reset; ++static const struct regmap_config sun20i_d1_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL, + }; + + static const struct sun4i_codec_quirks sun4i_codec_quirks = { + .regmap_config = &sun4i_codec_regmap_config, + .codec = &sun4i_codec_codec, + .create_card = sun4i_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, + }; +@@ -1597,7 +1769,11 @@ static const struct sun4i_codec_quirks s + .regmap_config = &sun6i_codec_regmap_config, + .codec = &sun6i_codec_codec, + .create_card = sun6i_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, +@@ -1607,7 +1783,11 @@ static const struct sun4i_codec_quirks s + .regmap_config = &sun7i_codec_regmap_config, + .codec = &sun7i_codec_codec, + .create_card = sun4i_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, + }; +@@ -1616,7 +1796,11 @@ static const struct sun4i_codec_quirks s + .regmap_config = &sun8i_a23_codec_regmap_config, + .codec = &sun8i_a23_codec_codec, + .create_card = sun8i_a23_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, +@@ -1631,7 +1815,11 @@ static const struct sun4i_codec_quirks s + */ + .codec = &sun8i_a23_codec_codec, + .create_card = sun8i_h3_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, +@@ -1645,12 +1833,31 @@ static const struct sun4i_codec_quirks s + */ + .codec = &sun8i_a23_codec_codec, + .create_card = sun8i_v3s_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, + }; + ++static const struct sun4i_codec_quirks sun20i_d1_codec_quirks = { ++ .regmap_config = &sun20i_d1_codec_regmap_config, ++ .codec = &sun20i_d1_codec_codec, ++ .create_card = sun20i_d1_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN20I_D1_CODEC_DAC_FIFOC, 0, 31), ++ .reg_adc_fifoc = REG_FIELD(SUN20I_D1_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, ++ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, ++ .reg_adc_rxdata = SUN20I_D1_CODEC_ADC_RXDATA, ++ .has_reset = true, ++ .has_dual_clock = true, ++}; ++ + static const struct of_device_id sun4i_codec_of_match[] = { + { + .compatible = "allwinner,sun4i-a10-codec", +@@ -1676,6 +1883,10 @@ static const struct of_device_id sun4i_c + .compatible = "allwinner,sun8i-v3s-codec", + .data = &sun8i_v3s_codec_quirks, + }, ++ { ++ .compatible = "allwinner,sun20i-d1-codec", ++ .data = &sun20i_d1_codec_quirks, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, sun4i_codec_of_match); +@@ -1704,6 +1915,7 @@ static int sun4i_codec_probe(struct plat + dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); + return -ENODEV; + } ++ scodec->quirks = quirks; + + scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, + quirks->regmap_config); +@@ -1719,10 +1931,24 @@ static int sun4i_codec_probe(struct plat + return PTR_ERR(scodec->clk_apb); + } + +- scodec->clk_module = devm_clk_get(&pdev->dev, "codec"); +- if (IS_ERR(scodec->clk_module)) { +- dev_err(&pdev->dev, "Failed to get the module clock\n"); +- return PTR_ERR(scodec->clk_module); ++ if (quirks->has_dual_clock) { ++ scodec->clk_module = devm_clk_get(&pdev->dev, "adc"); ++ if (IS_ERR(scodec->clk_module)) { ++ dev_err(&pdev->dev, "Failed to get the ADC module clock\n"); ++ return PTR_ERR(scodec->clk_module); ++ } ++ ++ scodec->clk_module_dac = devm_clk_get(&pdev->dev, "dac"); ++ if (IS_ERR(scodec->clk_module_dac)) { ++ dev_err(&pdev->dev, "Failed to get the DAC module clock\n"); ++ return PTR_ERR(scodec->clk_module_dac); ++ } ++ } else { ++ scodec->clk_module = devm_clk_get(&pdev->dev, "codec"); ++ if (IS_ERR(scodec->clk_module)) { ++ dev_err(&pdev->dev, "Failed to get the module clock\n"); ++ return PTR_ERR(scodec->clk_module); ++ } + } + + if (quirks->has_reset) { +@@ -1751,6 +1977,16 @@ static int sun4i_codec_probe(struct plat + dev_err(&pdev->dev, "Failed to create regmap fields: %d\n", + ret); + return ret; ++ } ++ ++ scodec->reg_dac_fifoc = devm_regmap_field_alloc(&pdev->dev, ++ scodec->regmap, ++ quirks->reg_dac_fifoc); ++ if (IS_ERR(scodec->reg_dac_fifoc)) { ++ ret = PTR_ERR(scodec->reg_dac_fifoc); ++ dev_err(&pdev->dev, "Failed to create regmap fields: %d\n", ++ ret); ++ return ret; + } + + /* Enable the bus clock */ diff --git a/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch b/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch new file mode 100644 index 00000000000..345504d3212 --- /dev/null +++ b/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch @@ -0,0 +1,274 @@ +From c8c3c516ca5c38e7858055ce0137efde17a07190 Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:04 +0300 +Subject: [PATCH 10/14] ASoC: sunxi: Add new driver for Allwinner D1/T113s + codec's analog path controls + +The internal codec on D1/T113s is split into 2 parts like the previous +ones. But now analog path controls registers are mapped directly +on the bus, right after the registers of the digital part. + +Add an ASoC component driver for it. This should be tied to the codec +audio card as an auxiliary device. + +Signed-off-by: Maksim Kiselev +--- + sound/soc/sunxi/Kconfig | 11 ++ + sound/soc/sunxi/Makefile | 1 + + sound/soc/sunxi/sun20i-d1-codec-analog.c | 220 +++++++++++++++++++++++ + 3 files changed, 232 insertions(+) + create mode 100644 sound/soc/sunxi/sun20i-d1-codec-analog.c + +--- a/sound/soc/sunxi/Kconfig ++++ b/sound/soc/sunxi/Kconfig +@@ -38,6 +38,17 @@ config SND_SUN50I_CODEC_ANALOG + Say Y or M if you want to add support for the analog controls for + the codec embedded in Allwinner A64 SoC. + ++config SND_SUN20I_D1_CODEC_ANALOG ++ tristate "Allwinner D1 Codec Analog Controls Support" ++ depends on ARCH_SUNXI || COMPILE_TEST ++ select REGMAP_MMIO ++ help ++ This option enables the analog controls part of the internal audio ++ codec for Allwinner D1/T113s SoCs family. ++ ++ Say Y or M if you want to add support for the analog part of ++ the D1/T113s audio codec. ++ + config SND_SUN4I_I2S + tristate "Allwinner A10 I2S Support" + select SND_SOC_GENERIC_DMAENGINE_PCM +--- a/sound/soc/sunxi/Makefile ++++ b/sound/soc/sunxi/Makefile +@@ -4,6 +4,7 @@ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s + obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o + obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o + obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o ++obj-$(CONFIG_SND_SUN20I_D1_CODEC_ANALOG) += sun20i-d1-codec-analog.o + obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o + obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o + obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o +--- /dev/null ++++ b/sound/soc/sunxi/sun20i-d1-codec-analog.c +@@ -0,0 +1,220 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * This driver supports the analog controls for the internal codec ++ * found in Allwinner's D1/T113s SoCs family. ++ * ++ * Based on sun50i-codec-analog.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++/* Codec analog control register offsets and bit fields */ ++#define SUN20I_D1_ADDA_ADC1 (0x00) ++#define SUN20I_D1_ADDA_ADC2 (0x04) ++#define SUN20I_D1_ADDA_ADC3 (0x08) ++#define SUN20I_D1_ADDA_ADC_EN (31) ++#define SUN20I_D1_ADDA_ADC_PGA_EN (30) ++#define SUN20I_D1_ADDA_ADC_MIC_SIN_EN (28) ++#define SUN20I_D1_ADDA_ADC_LINEINLEN (23) ++#define SUN20I_D1_ADDA_ADC_PGA_GAIN (8) ++ ++#define SUN20I_D1_ADDA_DAC (0x10) ++#define SUN20I_D1_ADDA_DAC_DACL_EN (15) ++#define SUN20I_D1_ADDA_DAC_DACR_EN (14) ++ ++#define SUN20I_D1_ADDA_MICBIAS (0x18) ++#define SUN20I_D1_ADDA_MICBIAS_MMICBIASEN (7) ++ ++#define SUN20I_D1_ADDA_RAMP (0x1C) ++#define SUN20I_D1_ADDA_RAMP_RD_EN (0) ++ ++#define SUN20I_D1_ADDA_HP2 (0x40) ++#define SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN (28) ++ ++#define SUN20I_D1_ADDA_ADC_CUR_REG (0x4C) ++ ++static const DECLARE_TLV_DB_RANGE(sun20i_d1_codec_adc_gain_scale, ++ 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), ++ 1, 3, TLV_DB_SCALE_ITEM(600, 0, 0), ++ 4, 4, TLV_DB_SCALE_ITEM(900, 0, 0), ++ 5, 31, TLV_DB_SCALE_ITEM(1000, 100, 0), ++); ++ ++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_hp_vol_scale, -4200, 600, 0); ++ ++/* volume controls */ ++static const struct snd_kcontrol_new sun20i_d1_codec_controls[] = { ++ SOC_SINGLE_TLV("Headphone Playback Volume", ++ SUN20I_D1_ADDA_HP2, ++ SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN, 0x7, 1, ++ sun20i_d1_codec_hp_vol_scale), ++ SOC_SINGLE_TLV("ADC1 Gain Capture Volume", ++ SUN20I_D1_ADDA_ADC1, ++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0, ++ sun20i_d1_codec_adc_gain_scale), ++ SOC_SINGLE_TLV("ADC2 Gain Capture Volume", ++ SUN20I_D1_ADDA_ADC2, ++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0, ++ sun20i_d1_codec_adc_gain_scale), ++ SOC_SINGLE_TLV("ADC3 Gain Capture Volume", ++ SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0, ++ sun20i_d1_codec_adc_gain_scale), ++}; ++ ++/* ADC mixer controls */ ++static const struct snd_kcontrol_new sun20i_d1_codec_mixer_controls[] = { ++ SOC_DAPM_DOUBLE_R("Line In Switch", ++ SUN20I_D1_ADDA_ADC1, ++ SUN20I_D1_ADDA_ADC2, ++ SUN20I_D1_ADDA_ADC_LINEINLEN, 1, 0), ++}; ++ ++static const char * const sun20i_d1_codec_mic3_src_enum_text[] = { ++ "Differential", "Single", ++}; ++ ++static SOC_ENUM_SINGLE_DECL(sun20i_d1_codec_mic3_src_enum, ++ SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_MIC_SIN_EN, ++ sun20i_d1_codec_mic3_src_enum_text); ++ ++static const struct snd_kcontrol_new sun20i_d1_codec_mic3_input_src[] = { ++ SOC_DAPM_ENUM("MIC3 Source Capture Route", ++ sun20i_d1_codec_mic3_src_enum), ++}; ++ ++static const struct snd_soc_dapm_widget sun20i_d1_codec_widgets[] = { ++ /* DAC */ ++ SND_SOC_DAPM_DAC("Left DAC", NULL, SUN20I_D1_ADDA_DAC, ++ SUN20I_D1_ADDA_DAC_DACL_EN, 0), ++ SND_SOC_DAPM_DAC("Right DAC", NULL, SUN20I_D1_ADDA_DAC, ++ SUN20I_D1_ADDA_DAC_DACR_EN, 0), ++ /* ADC */ ++ SND_SOC_DAPM_ADC("ADC1", NULL, SUN20I_D1_ADDA_ADC1, ++ SUN20I_D1_ADDA_ADC_EN, 0), ++ SND_SOC_DAPM_ADC("ADC2", NULL, SUN20I_D1_ADDA_ADC2, ++ SUN20I_D1_ADDA_ADC_EN, 0), ++ SND_SOC_DAPM_ADC("ADC3", NULL, SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_EN, 0), ++ ++ /* ADC Mixers */ ++ SND_SOC_DAPM_MIXER("ADC1 Mixer", SND_SOC_NOPM, 0, 0, ++ sun20i_d1_codec_mixer_controls, ++ ARRAY_SIZE(sun20i_d1_codec_mixer_controls)), ++ SND_SOC_DAPM_MIXER("ADC2 Mixer", SND_SOC_NOPM, 0, 0, ++ sun20i_d1_codec_mixer_controls, ++ ARRAY_SIZE(sun20i_d1_codec_mixer_controls)), ++ ++ /* Headphone */ ++ SND_SOC_DAPM_OUTPUT("HP"), ++ SND_SOC_DAPM_SUPPLY("RAMP Enable", SUN20I_D1_ADDA_RAMP, ++ SUN20I_D1_ADDA_RAMP_RD_EN, 0, NULL, 0), ++ ++ /* Line input */ ++ SND_SOC_DAPM_INPUT("LINEIN"), ++ ++ /* Microphone input */ ++ SND_SOC_DAPM_INPUT("MIC3"), ++ ++ /* Microphone input path */ ++ SND_SOC_DAPM_MUX("MIC3 Source Capture Route", SND_SOC_NOPM, 0, 0, ++ sun20i_d1_codec_mic3_input_src), ++ ++ SND_SOC_DAPM_PGA("Mic3 Amplifier", SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_PGA_EN, 0, NULL, 0), ++ ++ /* Microphone Bias */ ++ SND_SOC_DAPM_SUPPLY("MBIAS", SUN20I_D1_ADDA_MICBIAS, ++ SUN20I_D1_ADDA_MICBIAS_MMICBIASEN, 0, NULL, 0), ++}; ++ ++static const struct snd_soc_dapm_route sun20i_d1_codec_routes[] = { ++ /* Headphone Routes */ ++ { "HP", NULL, "Left DAC" }, ++ { "HP", NULL, "Right DAC" }, ++ { "HP", NULL, "RAMP Enable" }, ++ ++ /* Line input Routes */ ++ { "ADC1", NULL, "ADC1 Mixer" }, ++ { "ADC2", NULL, "ADC2 Mixer" }, ++ { "ADC1 Mixer", "Line In Switch", "LINEIN" }, ++ { "ADC2 Mixer", "Line In Switch", "LINEIN" }, ++ ++ /* Microphone Routes */ ++ { "MIC3 Source Capture Route", "Differential", "MIC3" }, ++ { "MIC3 Source Capture Route", "Single", "MIC3" }, ++ { "Mic3 Amplifier", NULL, "MIC3 Source Capture Route" }, ++ { "ADC3", NULL, "Mic3 Amplifier" }, ++}; ++ ++static const struct snd_soc_component_driver sun20i_d1_codec_analog_cmpnt_drv = { ++ .controls = sun20i_d1_codec_controls, ++ .num_controls = ARRAY_SIZE(sun20i_d1_codec_controls), ++ .dapm_widgets = sun20i_d1_codec_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(sun20i_d1_codec_widgets), ++ .dapm_routes = sun20i_d1_codec_routes, ++ .num_dapm_routes = ARRAY_SIZE(sun20i_d1_codec_routes), ++}; ++ ++static const struct of_device_id sun20i_d1_codec_analog_of_match[] = { ++ { ++ .compatible = "allwinner,sun20i-d1-codec-analog", ++ }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, sun20i_d1_codec_analog_of_match); ++ ++static const struct regmap_config sun20i_d1_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUN20I_D1_ADDA_ADC_CUR_REG, ++}; ++ ++static int sun20i_d1_codec_analog_probe(struct platform_device *pdev) ++{ ++ struct regmap *regmap; ++ void __iomem *base; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) { ++ dev_err(&pdev->dev, "Failed to map the registers\n"); ++ return PTR_ERR(base); ++ } ++ ++ regmap = devm_regmap_init_mmio(&pdev->dev, base, ++ &sun20i_d1_codec_regmap_config); ++ if (IS_ERR(regmap)) { ++ dev_err(&pdev->dev, "Failed to create regmap\n"); ++ return PTR_ERR(regmap); ++ } ++ ++ return devm_snd_soc_register_component(&pdev->dev, ++ &sun20i_d1_codec_analog_cmpnt_drv, ++ NULL, 0); ++} ++ ++static struct platform_driver sun20i_d1_codec_analog_driver = { ++ .driver = { ++ .name = "sun20i-d1-codec-analog", ++ .of_match_table = sun20i_d1_codec_analog_of_match, ++ }, ++ .probe = sun20i_d1_codec_analog_probe, ++}; ++module_platform_driver(sun20i_d1_codec_analog_driver); ++ ++MODULE_DESCRIPTION("Allwinner internal codec analog controls driver for D1"); ++MODULE_AUTHOR("Maksim Kiselev "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:sun20i-d1-codec-analog"); diff --git a/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch b/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch new file mode 100644 index 00000000000..06bd159998f --- /dev/null +++ b/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch @@ -0,0 +1,51 @@ +From 16728b748a44f1cea060a6ba57453c03e3745c1d Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Mon, 18 Dec 2023 00:06:22 +0300 +Subject: [PATCH 11/14] dt-bindings: thermal: sun8i: Add binding for D1/T113s + THS controller + +Add a binding for D1/T113s thermal sensor controller. + +Signed-off-by: Maxim Kiselev +Reviewed-by: Conor Dooley +--- + .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml ++++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +@@ -16,6 +16,7 @@ properties: + - allwinner,sun8i-a83t-ths + - allwinner,sun8i-h3-ths + - allwinner,sun8i-r40-ths ++ - allwinner,sun20i-d1-ths + - allwinner,sun50i-a64-ths + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h5-ths +@@ -61,6 +62,7 @@ allOf: + compatible: + contains: + enum: ++ - allwinner,sun20i-d1-ths + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h6-ths + +@@ -84,7 +86,9 @@ allOf: + properties: + compatible: + contains: +- const: allwinner,sun8i-h3-ths ++ enum: ++ - allwinner,sun8i-h3-ths ++ - allwinner,sun20i-d1-ths + + then: + properties: +@@ -103,6 +107,7 @@ allOf: + enum: + - allwinner,sun8i-h3-ths + - allwinner,sun8i-r40-ths ++ - allwinner,sun20i-d1-ths + - allwinner,sun50i-a64-ths + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h5-ths diff --git a/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch b/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch new file mode 100644 index 00000000000..a7ded598688 --- /dev/null +++ b/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch @@ -0,0 +1,45 @@ +From eb7e78f9e4bb9133898875afb0e0b9f09663e802 Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Mon, 18 Dec 2023 00:06:23 +0300 +Subject: [PATCH 12/14] thermal: sun8i: Add D1/T113s THS controller support + +This patch adds a thermal sensor controller support for the D1/T113s, +which is similar to the one on H6, but with only one sensor and +different scale and offset values. + +Signed-off-by: Maxim Kiselev +Reviewed-by: Andre Przywara +Acked-by: Jernej Skrabec +--- + drivers/thermal/sun8i_thermal.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/drivers/thermal/sun8i_thermal.c ++++ b/drivers/thermal/sun8i_thermal.c +@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun + .calc_temp = sun8i_ths_calc_temp, + }; + ++static const struct ths_thermal_chip sun20i_d1_ths = { ++ .sensor_num = 1, ++ .has_bus_clk_reset = true, ++ .offset = 188552, ++ .scale = 673, ++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, ++ .calibrate = sun50i_h6_ths_calibrate, ++ .init = sun50i_h6_thermal_init, ++ .irq_ack = sun50i_h6_irq_ack, ++ .calc_temp = sun8i_ths_calc_temp, ++}; ++ + static const struct of_device_id of_ths_match[] = { + { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, + { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, +@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_ + { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths }, + { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, + { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, ++ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, of_ths_match); diff --git a/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch b/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch new file mode 100644 index 00000000000..f8318c82070 --- /dev/null +++ b/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch @@ -0,0 +1,47 @@ +From 196423a17b92ef241766691b42dac0136342bdb5 Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Mon, 18 Dec 2023 00:06:24 +0300 +Subject: [PATCH 13/14] riscv: dts: allwinner: d1: Add thermal sensor + +This patch adds a thermal sensor controller node for the D1/T113s. +Also it adds a THS calibration data cell to efuse node. + +Signed-off-by: Maxim Kiselev +Reviewed-by: Andre Przywara +--- + .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -166,6 +166,19 @@ + #io-channel-cells = <1>; + }; + ++ ths: thermal-sensor@2009400 { ++ compatible = "allwinner,sun20i-d1-ths"; ++ reg = <0x02009400 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_THS>; ++ clock-names = "bus"; ++ resets = <&ccu RST_BUS_THS>; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ status = "disabled"; ++ #thermal-sensor-cells = <0>; ++ }; ++ + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic"; +@@ -415,6 +428,10 @@ + reg = <0x3006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ ths_calibration: thermal-sensor-calibration@14 { ++ reg = <0x14 0x4>; ++ }; + }; + + crypto: crypto@3040000 { diff --git a/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch b/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch new file mode 100644 index 00000000000..14a4c3c131d --- /dev/null +++ b/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch @@ -0,0 +1,44 @@ +From edebcc9d47f0bfe9bd769a2c578dda16acbfbef2 Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:05 +0300 +Subject: [PATCH 14/14] riscv: dts: allwinner: d1: Add device nodes for + internal audio codec + +Add DT nodes for the internal D1/T113s audio codec and its analog part. + +Signed-off-by: Maksim Kiselev +--- + .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -179,6 +179,28 @@ + #thermal-sensor-cells = <0>; + }; + ++ codec: codec@2030000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun20i-d1-codec"; ++ reg = <0x02030000 0x300>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_AUDIO>, ++ <&ccu CLK_AUDIO_ADC>, ++ <&ccu CLK_AUDIO_DAC>; ++ clock-names = "apb", "adc", "dac"; ++ resets = <&ccu RST_BUS_AUDIO>; ++ dmas = <&dma 7>, <&dma 7>; ++ dma-names = "rx", "tx"; ++ allwinner,codec-analog-controls = <&codec_analog>; ++ status = "disabled"; ++ }; ++ ++ codec_analog: codec-analog@2030300 { ++ compatible = "allwinner,sun20i-d1-codec-analog"; ++ reg = <0x02030300 0xd00>; ++ status = "disabled"; ++ }; ++ + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic";