From: Varadarajan Narayanan <quic_varada@quicinc.com>
Date: Mon, 17 Mar 2025 10:00:26 +0000 (+0530)
Subject: dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
X-Git-Tag: v6.16-rc1~50^2~1^2~2
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a733e711278182840b4c9a0329294daa5cc34048;p=thirdparty%2Flinux.git

dt-bindings: PCI: qcom: Add MHI registers for IPQ9574

The MHI registers are present in IPQ5332, IPQ6018, IPQ8074 and IPQ9574
SoCs. Hence, add the MHI registers to the binding to allow these registers
to be defined in devicetree.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
[mani: commit message rewording]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250317100029.881286-2-quic_varada@quicinc.com
---

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index e20f142316cc1..9cc26d7822589 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -175,14 +175,16 @@ allOf:
       properties:
         reg:
           minItems: 5
-          maxItems: 5
+          maxItems: 6
         reg-names:
+          minItems: 5
           items:
             - const: dbi # DesignWare PCIe registers
             - const: elbi # External local bus interface registers
             - const: atu # ATU address space
             - const: parf # Qualcomm specific registers
             - const: config # PCIe configuration space
+            - const: mhi # MHI registers
 
   - if:
       properties: