From: John Madieu Date: Mon, 25 May 2026 11:02:13 +0000 (+0000) Subject: ASoC: dt-bindings: sound: Add DT binding for RZ/G3E sound X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a86fd3c202189876e8bc244c6e0be16a61f39d32;p=thirdparty%2Flinux.git ASoC: dt-bindings: sound: Add DT binding for RZ/G3E sound Add a standalone device tree binding for the Renesas RZ/G3E (R9A09G047) sound controller. The RZ/G3E sound IP is based on R-Car Sound but differs in several ways: - Uses unprefixed sub-node names (ssi, ssiu, src, dvc, mix, ctu) instead of R-Car's rcar_sound,xxx prefixed names. - Supports up to 5 DMA controllers per direction, allowing multiple DMA entries with repeated channel names in SSIU, SRC and DVC sub-nodes. - Has 47 clocks including per-SSI ADG clocks (adg-ssi-[0-9]), SCU clocks (scu, scu_x2, scu_supply), SSIF supply clock, AUDMAC peri-peri clock, and ADG clock. - Has 14 reset lines including SCU, ADG and AUDMAC peri-peri resets. - SSI operates exclusively in BUSIF mode. These differences make the RZ/G3E binding incompatible with the existing renesas,rsnd.yaml, so it is added as a separate standalone binding with its own $ref to dai-common.yaml. Signed-off-by: John Madieu Acked-by: Kuninori Morimoto Link: https://patch.msgid.link/20260525110230.4014435-2-john.madieu.xa@bp.renesas.com Signed-off-by: Mark Brown --- diff --git a/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml b/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml new file mode 100644 index 0000000000000..d7fa165546985 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml @@ -0,0 +1,800 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/renesas,r9a09g047-sound.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E Sound Controller + +maintainers: + - Kuninori Morimoto + - John Madieu + +description: + The RZ/G3E (R9A09G047) sound controller is based on R-Car Sound IP + with extended DMA channel support (up to 5 DMACs per direction), + additional clock domains (47 clocks including per-SSI ADG clocks), + and additional reset lines (14 including SCU, ADG and Audio DMAC + peri-peri resets). SSI operates exclusively in BUSIF mode with + 2-4 BUSIF channels per SSI. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: renesas,r9a09g047-sound + + reg: + maxItems: 5 + + reg-names: + items: + - const: scu + - const: adg + - const: ssiu + - const: ssi + - const: audmapp + + "#sound-dai-cells": + const: 1 + + "#clock-cells": + const: 0 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + maxItems: 47 + + clock-names: + items: + - const: ssi-all + - const: ssi-0 + - const: ssi-1 + - const: ssi-2 + - const: ssi-3 + - const: ssi-4 + - const: ssi-5 + - const: ssi-6 + - const: ssi-7 + - const: ssi-8 + - const: ssi-9 + - const: src-0 + - const: src-1 + - const: src-2 + - const: src-3 + - const: src-4 + - const: src-5 + - const: src-6 + - const: src-7 + - const: src-8 + - const: src-9 + - const: mix-0 + - const: mix-1 + - const: ctu-0 + - const: ctu-1 + - const: dvc-0 + - const: dvc-1 + - const: audio-clka + - const: audio-clkb + - const: audio-clkc + - const: audio-clki + - const: ssif_supply + - const: scu + - const: scu_x2 + - const: scu_supply + - const: adg-ssi-0 + - const: adg-ssi-1 + - const: adg-ssi-2 + - const: adg-ssi-3 + - const: adg-ssi-4 + - const: adg-ssi-5 + - const: adg-ssi-6 + - const: adg-ssi-7 + - const: adg-ssi-8 + - const: adg-ssi-9 + - const: audmapp + - const: adg + + power-domains: + maxItems: 1 + + resets: + maxItems: 14 + + reset-names: + items: + - const: ssi-all + - const: ssi-0 + - const: ssi-1 + - const: ssi-2 + - const: ssi-3 + - const: ssi-4 + - const: ssi-5 + - const: ssi-6 + - const: ssi-7 + - const: ssi-8 + - const: ssi-9 + - const: scu + - const: adg + - const: audmapp + + dvc: + type: object + additionalProperties: false + + patternProperties: + "^dvc-[0-1]$": + type: object + additionalProperties: false + + properties: + dmas: + maxItems: 5 + description: + List of references to DMA specifiers, one per DMA + controller, all for the transmission direction + (DVC is playback-only). The dma-engine core falls + through the list to find a free channel. + + dma-names: + maxItems: 5 + allOf: + - items: + enum: + - tx + + required: + - dmas + - dma-names + + mix: + type: object + additionalProperties: false + description: + Per-channel Mixer (MIX) sub-nodes. Each mix-N node has no + properties of its own. It exists so the driver can enumerate + the MIX instances and so that DT labels can be attached to it + for the dai/playback/capture phandle routing arrays. + + patternProperties: + "^mix-[0-1]$": + type: object + additionalProperties: false + + ctu: + type: object + additionalProperties: false + description: + Per-channel Channel Transfer Unit (CTU) sub-nodes. Each ctu-N + node has no properties of its own. It exists so the driver + can enumerate the CTU instances and so that DT labels can be + attached to it for the dai/playback/capture phandle routing arrays. + + patternProperties: + "^ctu-[0-7]$": + type: object + additionalProperties: false + + src: + type: object + additionalProperties: false + + patternProperties: + "^src-[0-9]$": + type: object + additionalProperties: false + + properties: + interrupts: + maxItems: 1 + + dmas: + maxItems: 10 + description: + Must contain a list of pairs of references to DMA + specifiers, one for transmission and one for reception, + repeated for each DMA controller. The dma-engine core + falls through the list to find a free channel. + + dma-names: + maxItems: 10 + allOf: + - items: + enum: + - tx + - rx + + ssiu: + type: object + additionalProperties: false + + patternProperties: + "^ssiu-[0-9]+$": + type: object + additionalProperties: false + + properties: + dmas: + maxItems: 10 + description: + Must contain a list of pairs of references to DMA + specifiers, one for transmission and one for reception, + repeated for each DMA controller. The dma-engine core + falls through the list to find a free channel. + + dma-names: + maxItems: 10 + allOf: + - items: + enum: + - tx + - rx + + required: + - dmas + - dma-names + + ssi: + type: object + additionalProperties: false + + patternProperties: + "^ssi-[0-9]$": + type: object + additionalProperties: false + + properties: + interrupts: + maxItems: 1 + + shared-pin: + description: Shared clock pin. + $ref: /schemas/types.yaml#/definitions/flag + + required: + - interrupts + + ports: + $ref: audio-graph-port.yaml#/definitions/port-base + unevaluatedProperties: false + patternProperties: + '^port@[0-9a-f]+$': + $ref: audio-graph-port.yaml#/definitions/port-base + unevaluatedProperties: false + properties: + reg: + maxItems: 1 + endpoint: + $ref: audio-graph-port.yaml#/definitions/endpoint-base + unevaluatedProperties: false + properties: + playback: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Ordered list of phandles to the in-SoC modules used + by this DAI in the playback direction. Each phandle + must reference one of the ssi-N, src-N, ctu-N, + mix-N or dvc-N sub-nodes of the parent sound + controller. The list order is the pipeline order + from CPU to off-SoC endpoint. + capture: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Ordered list of phandles to the in-SoC modules used + by this DAI in the capture direction. Each phandle + must reference one of the ssi-N, src-N, ctu-N, + mix-N or dvc-N sub-nodes of the parent sound + controller. The list order is the pipeline order + from off-SoC endpoint to CPU. + +required: + - compatible + - reg + - reg-names + - "#sound-dai-cells" + - "#clock-cells" + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + + sound@13c00000 { + #sound-dai-cells = <1>; + #clock-cells = <0>; + compatible = "renesas,r9a09g047-sound"; + reg = <0x13c00000 0x10000>, + <0x13c20000 0x10000>, + <0x13c30000 0x1000>, + <0x13c31000 0x1f000>, + <0x13c50000 0x10000>; + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&cpg 245>, + <&cpg 385>, <&cpg 386>, + <&cpg 387>, <&cpg 388>, + <&cpg 389>, <&cpg 390>, + <&cpg 391>, <&cpg 392>, + <&cpg 393>, <&cpg 394>, + <&cpg 372>, <&cpg 373>, + <&cpg 374>, <&cpg 375>, + <&cpg 376>, <&cpg 377>, + <&cpg 378>, <&cpg 379>, + <&cpg 380>, <&cpg 381>, + <&cpg 370>, <&cpg 371>, + <&cpg 370>, <&cpg 371>, + <&cpg 368>, <&cpg 369>, + <&cpg 251>, <&cpg 252>, + <&cpg 253>, <&cpg 250>, + <&cpg 384>, + <&cpg 246>, <&cpg 247>, + <&cpg 382>, + <&cpg 352>, <&cpg 353>, + <&cpg 354>, <&cpg 355>, + <&cpg 356>, <&cpg 357>, + <&cpg 358>, <&cpg 359>, + <&cpg 360>, <&cpg 361>, + <&cpg 248>, <&cpg 249>; + clock-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "src-0", "src-1", + "src-2", "src-3", + "src-4", "src-5", + "src-6", "src-7", + "src-8", "src-9", + "mix-0", "mix-1", + "ctu-0", "ctu-1", + "dvc-0", "dvc-1", + "audio-clka", "audio-clkb", + "audio-clkc", "audio-clki", + "ssif_supply", + "scu", "scu_x2", + "scu_supply", + "adg-ssi-0", "adg-ssi-1", + "adg-ssi-2", "adg-ssi-3", + "adg-ssi-4", "adg-ssi-5", + "adg-ssi-6", "adg-ssi-7", + "adg-ssi-8", "adg-ssi-9", + "audmapp", "adg"; + power-domains = <&cpg>; + resets = <&cpg 225>, + <&cpg 226>, <&cpg 227>, + <&cpg 228>, <&cpg 229>, + <&cpg 230>, <&cpg 231>, + <&cpg 232>, <&cpg 233>, + <&cpg 234>, <&cpg 235>, + <&cpg 236>, <&cpg 238>, <&cpg 237>; + reset-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "scu", "adg", + "audmapp"; + + ctu { + ctu-0 { }; + ctu-1 { }; + ctu-2 { }; + ctu-3 { }; + ctu-4 { }; + ctu-5 { }; + ctu-6 { }; + ctu-7 { }; + }; + + dvc { + dvc0: dvc-0 { + dmas = <&dmac0 0x1db3>, <&dmac1 0x1db3>, + <&dmac2 0x1db3>, <&dmac3 0x1db3>, + <&dmac4 0x1db3>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + dvc1: dvc-1 { + dmas = <&dmac0 0x1db4>, <&dmac1 0x1db4>, + <&dmac2 0x1db4>, <&dmac3 0x1db4>, + <&dmac4 0x1db4>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + }; + + mix { + mix-0 { }; + mix-1 { }; + }; + + src { + src0: src-0 { + interrupts = ; + dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>, + <&dmac1 0x1d9f>, <&dmac1 0x1da9>, + <&dmac2 0x1d9f>, <&dmac2 0x1da9>, + <&dmac3 0x1d9f>, <&dmac3 0x1da9>, + <&dmac4 0x1d9f>, <&dmac4 0x1da9>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>, + <&dmac1 0x1da0>, <&dmac1 0x1daa>, + <&dmac2 0x1da0>, <&dmac2 0x1daa>, + <&dmac3 0x1da0>, <&dmac3 0x1daa>, + <&dmac4 0x1da0>, <&dmac4 0x1daa>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-2 { + interrupts = ; + dmas = <&dmac0 0x1da1>, <&dmac0 0x1dab>, + <&dmac1 0x1da1>, <&dmac1 0x1dab>, + <&dmac2 0x1da1>, <&dmac2 0x1dab>, + <&dmac3 0x1da1>, <&dmac3 0x1dab>, + <&dmac4 0x1da1>, <&dmac4 0x1dab>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-3 { + interrupts = ; + dmas = <&dmac0 0x1da2>, <&dmac0 0x1dac>, + <&dmac1 0x1da2>, <&dmac1 0x1dac>, + <&dmac2 0x1da2>, <&dmac2 0x1dac>, + <&dmac3 0x1da2>, <&dmac3 0x1dac>, + <&dmac4 0x1da2>, <&dmac4 0x1dac>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-4 { + interrupts = ; + dmas = <&dmac0 0x1da3>, <&dmac0 0x1dad>, + <&dmac1 0x1da3>, <&dmac1 0x1dad>, + <&dmac2 0x1da3>, <&dmac2 0x1dad>, + <&dmac3 0x1da3>, <&dmac3 0x1dad>, + <&dmac4 0x1da3>, <&dmac4 0x1dad>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-5 { + interrupts = ; + dmas = <&dmac0 0x1da4>, <&dmac0 0x1dae>, + <&dmac1 0x1da4>, <&dmac1 0x1dae>, + <&dmac2 0x1da4>, <&dmac2 0x1dae>, + <&dmac3 0x1da4>, <&dmac3 0x1dae>, + <&dmac4 0x1da4>, <&dmac4 0x1dae>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-6 { + interrupts = ; + dmas = <&dmac0 0x1da5>, <&dmac0 0x1daf>, + <&dmac1 0x1da5>, <&dmac1 0x1daf>, + <&dmac2 0x1da5>, <&dmac2 0x1daf>, + <&dmac3 0x1da5>, <&dmac3 0x1daf>, + <&dmac4 0x1da5>, <&dmac4 0x1daf>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-7 { + interrupts = ; + dmas = <&dmac0 0x1da6>, <&dmac0 0x1db0>, + <&dmac1 0x1da6>, <&dmac1 0x1db0>, + <&dmac2 0x1da6>, <&dmac2 0x1db0>, + <&dmac3 0x1da6>, <&dmac3 0x1db0>, + <&dmac4 0x1da6>, <&dmac4 0x1db0>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-8 { + interrupts = ; + dmas = <&dmac0 0x1da7>, <&dmac0 0x1db1>, + <&dmac1 0x1da7>, <&dmac1 0x1db1>, + <&dmac2 0x1da7>, <&dmac2 0x1db1>, + <&dmac3 0x1da7>, <&dmac3 0x1db1>, + <&dmac4 0x1da7>, <&dmac4 0x1db1>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-9 { + interrupts = ; + dmas = <&dmac0 0x1da8>, <&dmac0 0x1db2>, + <&dmac1 0x1da8>, <&dmac1 0x1db2>, + <&dmac2 0x1da8>, <&dmac2 0x1db2>, + <&dmac3 0x1da8>, <&dmac3 0x1db2>, + <&dmac4 0x1da8>, <&dmac4 0x1db2>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + }; + + ssi { + ssi-0 { + interrupts = ; + }; + ssi-1 { + interrupts = ; + }; + ssi-2 { + interrupts = ; + }; + ssi3: ssi-3 { + interrupts = ; + }; + ssi4: ssi-4 { + interrupts = ; + shared-pin; + }; + ssi-5 { + interrupts = ; + }; + ssi-6 { + interrupts = ; + }; + ssi-7 { + interrupts = ; + }; + ssi-8 { + interrupts = ; + }; + ssi-9 { + interrupts = ; + }; + }; + + ssiu { + ssiu-0 { + dmas = <&dmac0 0x1d61>, <&dmac0 0x1d62>, + <&dmac1 0x1d61>, <&dmac1 0x1d62>, + <&dmac2 0x1d61>, <&dmac2 0x1d62>, + <&dmac3 0x1d61>, <&dmac3 0x1d62>, + <&dmac4 0x1d61>, <&dmac4 0x1d62>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-1 { + dmas = <&dmac0 0x1d63>, <&dmac0 0x1d64>, + <&dmac1 0x1d63>, <&dmac1 0x1d64>, + <&dmac2 0x1d63>, <&dmac2 0x1d64>, + <&dmac3 0x1d63>, <&dmac3 0x1d64>, + <&dmac4 0x1d63>, <&dmac4 0x1d64>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-2 { + dmas = <&dmac0 0x1d65>, <&dmac0 0x1d66>, + <&dmac1 0x1d65>, <&dmac1 0x1d66>, + <&dmac2 0x1d65>, <&dmac2 0x1d66>, + <&dmac3 0x1d65>, <&dmac3 0x1d66>, + <&dmac4 0x1d65>, <&dmac4 0x1d66>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-3 { + dmas = <&dmac0 0x1d67>, <&dmac0 0x1d68>, + <&dmac1 0x1d67>, <&dmac1 0x1d68>, + <&dmac2 0x1d67>, <&dmac2 0x1d68>, + <&dmac3 0x1d67>, <&dmac3 0x1d68>, + <&dmac4 0x1d67>, <&dmac4 0x1d68>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-4 { + dmas = <&dmac0 0x1d69>, <&dmac0 0x1d6a>, + <&dmac1 0x1d69>, <&dmac1 0x1d6a>, + <&dmac2 0x1d69>, <&dmac2 0x1d6a>, + <&dmac3 0x1d69>, <&dmac3 0x1d6a>, + <&dmac4 0x1d69>, <&dmac4 0x1d6a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-5 { + dmas = <&dmac0 0x1d6b>, <&dmac0 0x1d6c>, + <&dmac1 0x1d6b>, <&dmac1 0x1d6c>, + <&dmac2 0x1d6b>, <&dmac2 0x1d6c>, + <&dmac3 0x1d6b>, <&dmac3 0x1d6c>, + <&dmac4 0x1d6b>, <&dmac4 0x1d6c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-6 { + dmas = <&dmac0 0x1d6d>, <&dmac0 0x1d6e>, + <&dmac1 0x1d6d>, <&dmac1 0x1d6e>, + <&dmac2 0x1d6d>, <&dmac2 0x1d6e>, + <&dmac3 0x1d6d>, <&dmac3 0x1d6e>, + <&dmac4 0x1d6d>, <&dmac4 0x1d6e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-7 { + dmas = <&dmac0 0x1d6f>, <&dmac0 0x1d70>, + <&dmac1 0x1d6f>, <&dmac1 0x1d70>, + <&dmac2 0x1d6f>, <&dmac2 0x1d70>, + <&dmac3 0x1d6f>, <&dmac3 0x1d70>, + <&dmac4 0x1d6f>, <&dmac4 0x1d70>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-8 { + dmas = <&dmac0 0x1d71>, <&dmac0 0x1d72>, + <&dmac1 0x1d71>, <&dmac1 0x1d72>, + <&dmac2 0x1d71>, <&dmac2 0x1d72>, + <&dmac3 0x1d71>, <&dmac3 0x1d72>, + <&dmac4 0x1d71>, <&dmac4 0x1d72>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-9 { + dmas = <&dmac0 0x1d73>, <&dmac0 0x1d74>, + <&dmac1 0x1d73>, <&dmac1 0x1d74>, + <&dmac2 0x1d73>, <&dmac2 0x1d74>, + <&dmac3 0x1d73>, <&dmac3 0x1d74>, + <&dmac4 0x1d73>, <&dmac4 0x1d74>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-10 { + dmas = <&dmac0 0x1d75>, <&dmac0 0x1d76>, + <&dmac1 0x1d75>, <&dmac1 0x1d76>, + <&dmac2 0x1d75>, <&dmac2 0x1d76>, + <&dmac3 0x1d75>, <&dmac3 0x1d76>, + <&dmac4 0x1d75>, <&dmac4 0x1d76>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-11 { + dmas = <&dmac0 0x1d77>, <&dmac0 0x1d78>, + <&dmac1 0x1d77>, <&dmac1 0x1d78>, + <&dmac2 0x1d77>, <&dmac2 0x1d78>, + <&dmac3 0x1d77>, <&dmac3 0x1d78>, + <&dmac4 0x1d77>, <&dmac4 0x1d78>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-12 { + dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>, + <&dmac1 0x1d79>, <&dmac1 0x1d7a>, + <&dmac2 0x1d79>, <&dmac2 0x1d7a>, + <&dmac3 0x1d79>, <&dmac3 0x1d7a>, + <&dmac4 0x1d79>, <&dmac4 0x1d7a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-13 { + dmas = <&dmac0 0x1d7b>, <&dmac0 0x1d7c>, + <&dmac1 0x1d7b>, <&dmac1 0x1d7c>, + <&dmac2 0x1d7b>, <&dmac2 0x1d7c>, + <&dmac3 0x1d7b>, <&dmac3 0x1d7c>, + <&dmac4 0x1d7b>, <&dmac4 0x1d7c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-14 { + dmas = <&dmac0 0x1d7d>, <&dmac0 0x1d7e>, + <&dmac1 0x1d7d>, <&dmac1 0x1d7e>, + <&dmac2 0x1d7d>, <&dmac2 0x1d7e>, + <&dmac3 0x1d7d>, <&dmac3 0x1d7e>, + <&dmac4 0x1d7d>, <&dmac4 0x1d7e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-15 { + dmas = <&dmac0 0x1d7f>, <&dmac0 0x1d80>, + <&dmac1 0x1d7f>, <&dmac1 0x1d80>, + <&dmac2 0x1d7f>, <&dmac2 0x1d80>, + <&dmac3 0x1d7f>, <&dmac3 0x1d80>, + <&dmac4 0x1d7f>, <&dmac4 0x1d80>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-16 { + dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>, + <&dmac1 0x1d81>, <&dmac1 0x1d82>, + <&dmac2 0x1d81>, <&dmac2 0x1d82>, + <&dmac3 0x1d81>, <&dmac3 0x1d82>, + <&dmac4 0x1d81>, <&dmac4 0x1d82>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-17 { + dmas = <&dmac0 0x1d83>, <&dmac0 0x1d84>, + <&dmac1 0x1d83>, <&dmac1 0x1d84>, + <&dmac2 0x1d83>, <&dmac2 0x1d84>, + <&dmac3 0x1d83>, <&dmac3 0x1d84>, + <&dmac4 0x1d83>, <&dmac4 0x1d84>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-18 { + dmas = <&dmac0 0x1d85>, <&dmac0 0x1d86>, + <&dmac1 0x1d85>, <&dmac1 0x1d86>, + <&dmac2 0x1d85>, <&dmac2 0x1d86>, + <&dmac3 0x1d85>, <&dmac3 0x1d86>, + <&dmac4 0x1d85>, <&dmac4 0x1d86>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-19 { + dmas = <&dmac0 0x1d87>, <&dmac0 0x1d88>, + <&dmac1 0x1d87>, <&dmac1 0x1d88>, + <&dmac2 0x1d87>, <&dmac2 0x1d88>, + <&dmac3 0x1d87>, <&dmac3 0x1d88>, + <&dmac4 0x1d87>, <&dmac4 0x1d88>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-20 { + dmas = <&dmac0 0x1d89>, <&dmac0 0x1d8a>, + <&dmac1 0x1d89>, <&dmac1 0x1d8a>, + <&dmac2 0x1d89>, <&dmac2 0x1d8a>, + <&dmac3 0x1d89>, <&dmac3 0x1d8a>, + <&dmac4 0x1d89>, <&dmac4 0x1d8a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-21 { + dmas = <&dmac0 0x1d8b>, <&dmac0 0x1d8c>, + <&dmac1 0x1d8b>, <&dmac1 0x1d8c>, + <&dmac2 0x1d8b>, <&dmac2 0x1d8c>, + <&dmac3 0x1d8b>, <&dmac3 0x1d8c>, + <&dmac4 0x1d8b>, <&dmac4 0x1d8c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-22 { + dmas = <&dmac0 0x1d8d>, <&dmac0 0x1d8e>, + <&dmac1 0x1d8d>, <&dmac1 0x1d8e>, + <&dmac2 0x1d8d>, <&dmac2 0x1d8e>, + <&dmac3 0x1d8d>, <&dmac3 0x1d8e>, + <&dmac4 0x1d8d>, <&dmac4 0x1d8e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-23 { + dmas = <&dmac0 0x1d8f>, <&dmac0 0x1d90>, + <&dmac1 0x1d8f>, <&dmac1 0x1d90>, + <&dmac2 0x1d8f>, <&dmac2 0x1d90>, + <&dmac3 0x1d8f>, <&dmac3 0x1d90>, + <&dmac4 0x1d8f>, <&dmac4 0x1d90>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-24 { + dmas = <&dmac0 0x1d91>, <&dmac0 0x1d92>, + <&dmac1 0x1d91>, <&dmac1 0x1d92>, + <&dmac2 0x1d91>, <&dmac2 0x1d92>, + <&dmac3 0x1d91>, <&dmac3 0x1d92>, + <&dmac4 0x1d91>, <&dmac4 0x1d92>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-25 { + dmas = <&dmac0 0x1d93>, <&dmac0 0x1d94>, + <&dmac1 0x1d93>, <&dmac1 0x1d94>, + <&dmac2 0x1d93>, <&dmac2 0x1d94>, + <&dmac3 0x1d93>, <&dmac3 0x1d94>, + <&dmac4 0x1d93>, <&dmac4 0x1d94>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-26 { + dmas = <&dmac0 0x1d95>, <&dmac0 0x1d96>, + <&dmac1 0x1d95>, <&dmac1 0x1d96>, + <&dmac2 0x1d95>, <&dmac2 0x1d96>, + <&dmac3 0x1d95>, <&dmac3 0x1d96>, + <&dmac4 0x1d95>, <&dmac4 0x1d96>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-27 { + dmas = <&dmac0 0x1d97>, <&dmac0 0x1d98>, + <&dmac1 0x1d97>, <&dmac1 0x1d98>, + <&dmac2 0x1d97>, <&dmac2 0x1d98>, + <&dmac3 0x1d97>, <&dmac3 0x1d98>, + <&dmac4 0x1d97>, <&dmac4 0x1d98>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rsnd_endpoint0: endpoint { + remote-endpoint = <&codec_endpoint>; + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + playback = <&ssi3>, <&src1>, <&dvc1>; + capture = <&ssi4>, <&src0>, <&dvc0>; + }; + }; + }; + };