From: Andreas Arnez <arnez@linux.ibm.com>
Date: Thu, 26 Oct 2023 12:00:52 +0000 (+0200)
Subject: s390x regtest: Activate 128 bit SIMD tests for s390x in vbit-test
X-Git-Tag: VALGRIND_3_22_0~6
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a9014ef5f1ec84fb60abf67f8dc1a6fb9bf539f6;p=thirdparty%2Fvalgrind.git

s390x regtest: Activate 128 bit SIMD tests for s390x in vbit-test

The vbit-test test case is currently configured to exclude s390x from the
platforms that execute the 128 bit SIMD irop tests.  Since there's no
known issue with those, they can be activated on s390x as well.
---

diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index e94ea2432c..24f258bf0c 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -790,12 +790,12 @@ static irop_t irops[] = {
   { DEFOP(Iop_MulHi16Sx8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_MulHi32Sx4, UNDEF_UNKNOWN), },
   /* Result of the Iop_MullEvenBxE is 2*BxE/2 */
-  { DEFOP(Iop_MullEven8Ux16, UNDEF_ALL_8x16_EVEN), .ppc64 = 1, .ppc32 = 1 },
-  { DEFOP(Iop_MullEven16Ux8, UNDEF_ALL_16x8_EVEN), .ppc64 = 1, .ppc32 = 1 },
-  { DEFOP(Iop_MullEven32Ux4, UNDEF_ALL_32x4_EVEN), .ppc64 = 1, .ppc32 = 1 },
-  { DEFOP(Iop_MullEven8Sx16, UNDEF_ALL_8x16_EVEN), .ppc64 = 1, .ppc32 = 1 },
-  { DEFOP(Iop_MullEven16Sx8, UNDEF_ALL_16x8_EVEN), .ppc64 = 1, .ppc32 = 1 },
-  { DEFOP(Iop_MullEven32Sx4, UNDEF_ALL_32x4_EVEN), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_MullEven8Ux16, UNDEF_ALL_8x16_EVEN), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_MullEven16Ux8, UNDEF_ALL_16x8_EVEN), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_MullEven32Ux4, UNDEF_ALL_32x4_EVEN), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_MullEven8Sx16, UNDEF_ALL_8x16_EVEN), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_MullEven16Sx8, UNDEF_ALL_16x8_EVEN), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_MullEven32Sx4, UNDEF_ALL_32x4_EVEN), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_Mull8Ux8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Mull8Sx8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Mull16Ux4, UNDEF_UNKNOWN), },
@@ -837,19 +837,19 @@ static irop_t irops[] = {
   { DEFOP(Iop_Max8Sx16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Max16Sx8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Max32Sx4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_Max64Sx2, UNDEF_ALL_64x2), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_Max64Sx2, UNDEF_ALL_64x2), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_Max8Ux16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Max16Ux8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Max32Ux4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_Max64Ux2, UNDEF_ALL_64x2), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_Max64Ux2, UNDEF_ALL_64x2), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_Min8Sx16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Min16Sx8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Min32Sx4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_Min64Sx2, UNDEF_ALL_64x2), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_Min64Sx2, UNDEF_ALL_64x2), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_Min8Ux16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Min16Ux8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Min32Ux4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_Min64Ux2, UNDEF_ALL_64x2), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_Min64Ux2, UNDEF_ALL_64x2), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_CmpEQ8x16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_CmpEQ16x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_CmpEQ32x4, UNDEF_UNKNOWN), },
@@ -866,7 +866,7 @@ static irop_t irops[] = {
   { DEFOP(Iop_Clz8x16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Clz16x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Clz32x4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_Clz64x2, UNDEF_ALL_64x2), .ppc64 = 1, .ppc32 = 1  },
+  { DEFOP(Iop_Clz64x2, UNDEF_ALL_64x2), .s390x = 1, .ppc64 = 1, .ppc32 = 1  },
   { DEFOP(Iop_Ctz8x16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Ctz16x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Ctz32x4, UNDEF_UNKNOWN), },
@@ -905,7 +905,7 @@ static irop_t irops[] = {
   { DEFOP(Iop_Rol8x16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Rol16x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Rol32x4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_Rol64x2, UNDEF_64x2_ROTATE), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_Rol64x2, UNDEF_64x2_ROTATE), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_QShl8x16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QShl16x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QShl32x4, UNDEF_UNKNOWN), },
@@ -986,18 +986,18 @@ static irop_t irops[] = {
   { DEFOP(Iop_QNarrowBin32Uto16Ux8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_NarrowBin16to8x16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_NarrowBin32to16x8, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_NarrowBin64to32x4, UNDEF_NARROW256_AtoB), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_NarrowBin64to32x4, UNDEF_NARROW256_AtoB), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_NarrowUn16to8x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_NarrowUn32to16x4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_NarrowUn64to32x2, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QNarrowUn16Sto8Sx8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QNarrowUn32Sto16Sx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QNarrowUn64Sto32Sx2, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_QNarrowBin64Sto32Sx4, UNDEF_NARROW256_AtoB), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_QNarrowBin64Sto32Sx4, UNDEF_NARROW256_AtoB), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_QNarrowUn16Sto8Ux8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QNarrowUn32Sto16Ux4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QNarrowUn64Sto32Ux2, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_QNarrowBin64Uto32Ux4, UNDEF_NARROW256_AtoB), .ppc64 = 1, .ppc32 = 1 },
+  { DEFOP(Iop_QNarrowBin64Uto32Ux4, UNDEF_NARROW256_AtoB), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
   { DEFOP(Iop_QNarrowUn16Uto8Ux8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QNarrowUn32Uto16Ux4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_QNarrowUn64Uto32Ux2, UNDEF_UNKNOWN), },