From: Richard Earnshaw <rearnsha@arm.com>
Date: Mon, 19 Dec 2022 15:01:49 +0000 (+0000)
Subject: arm: correctly define __ARM_FEATURE_CLZ
X-Git-Tag: basepoints/gcc-14~2414
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=aa510619f8b650322c113d8593dd57afe6c6f9ae;p=thirdparty%2Fgcc.git

arm: correctly define __ARM_FEATURE_CLZ

The ACLE requires that __ARM_FEATURE_CLZ be defined if the hardware
supports it; it's also clear that this doesn't mean the current ISA,
so we must define this even when compiling for Thumb1 if the target
supports CLZ in A32.

This brings GCC into alignment with Clang.

gcc/ChangeLog:

	* config/arm/arm-c.cc (__ARM_FEATURE_CLZ): Fix definition of
	preprocessor macro when target has CLZ in another ISA.
---

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index 86c56bf26800..202898fa0418 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -238,8 +238,12 @@ arm_cpu_builtins (struct cpp_reader* pfile)
     builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
 				   TARGET_ARM_FEATURE_LDREX);
 
+  /* ACLE says that __ARM_FEATURE_CLZ is defined if the hardware
+     supports it; it's also clear that this doesn't mean the current
+     ISA, so we define this even when compiling for Thumb1 if the
+     target supports CLZ in A32.  */
   def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ",
-		      ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB)
+		      ((TARGET_ARM_ARCH >= 5 && arm_arch_notm)
 		       || TARGET_ARM_ARCH_ISA_THUMB >=2));
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",