From: Petar Jovanovic <mips32r2@gmail.com>
Date: Sat, 9 May 2026 13:46:27 +0000 (+0000)
Subject: [mips] fix CmpLE32U and Max32U ops
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=aa9e2013704a035c4cf31af8fc55028c50448647;p=thirdparty%2Fvalgrind.git

[mips] fix CmpLE32U and Max32U ops

CmpLE32U operation was incorrectly implemented as a signed comparaison,
use less-or-same for unsigned.

Max32U operation was incorrectly implemented using the SLT instruction,
use the unsigned variant SLTU.

This partially fixes none/tests/iropt-test.

Patch by:
Dimitrije Dzunic <dimitrije.dzunic@htecgroup.com>
Aleksandar Rikalo <aleksandar.rikalo@htecgroup.com>
---

diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c
index d018aac84..c14782ffd 100644
--- a/VEX/priv/host_mips_defs.c
+++ b/VEX/priv/host_mips_defs.c
@@ -795,6 +795,9 @@ const HChar *showMIPSAluOp(MIPSAluOp op, Bool immR)
       case Malu_SLT:
          ret = immR ? "slti" : "slt";
          break;
+      case Malu_SLTU:
+         ret = immR ? "sltui" : "sltu";
+         break;
       default:
          vpanic("showMIPSAluOp");
          break;
@@ -3885,6 +3888,13 @@ Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc,
                   p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 42);
                }
                break;
+            case Malu_SLTU:
+               if (immR) {
+                  goto bad;
+               } else {
+                  p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 43);
+               }
+               break;
 
             default:
                goto bad;
diff --git a/VEX/priv/host_mips_defs.h b/VEX/priv/host_mips_defs.h
index 838368b85..4aaec8900 100644
--- a/VEX/priv/host_mips_defs.h
+++ b/VEX/priv/host_mips_defs.h
@@ -268,7 +268,7 @@ typedef enum {
    Malu_ADD, Malu_SUB,
    Malu_AND, Malu_OR, Malu_NOR, Malu_XOR,
    Malu_DADD, Malu_DSUB,
-   Malu_SLT
+   Malu_SLT, Malu_SLTU
 } MIPSAluOp;
 
 extern const HChar *showMIPSAluOp(MIPSAluOp,
diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index 19c761b00..1260e0b7d 100644
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -1139,7 +1139,7 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
                   size32 = False;
                   break;
                case Iop_CmpLE32U:
-                  cc = MIPScc_LE;
+                  cc = MIPScc_LS;
                   size32 = True;
                   break;
                case Iop_CmpLE32S:
@@ -1175,10 +1175,10 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
             MIPSRH *argRH = MIPSRH_Reg(argR);
             /* max (v0, s0)
                ------------
-               slt v1, v0, s0
+               sltu v1, v0, s0
                movn v0, s0, v1 */
 
-            addInstr(env, MIPSInstr_Alu(Malu_SLT, tmp, argL, argRH));
+            addInstr(env, MIPSInstr_Alu(Malu_SLTU, tmp, argL, argRH));
 #if (__mips_isa_rev >= 6)
             {
               HReg r_temp  = newVRegI(env);