From: Julian Seward <jseward@acm.org>
Date: Mon, 10 Mar 2014 10:40:48 +0000 (+0000)
Subject: Back-end handling of Iop_CmpNEZ32x4, Iop_CmpNEZ16x8, Iop_CmpNEZ8x16,
X-Git-Tag: svn/VALGRIND_3_10_1^2~133
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=aab33563a1f3c6d5066fb4f192e3a596c5b7ec3e;p=thirdparty%2Fvalgrind.git

Back-end handling of Iop_CmpNEZ32x4, Iop_CmpNEZ16x8, Iop_CmpNEZ8x16,
needed for Memchecking of SIMD arm64 code.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2837
---

diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c
index 47b2df5370..a26f5771a6 100644
--- a/VEX/priv/host_arm64_defs.c
+++ b/VEX/priv/host_arm64_defs.c
@@ -882,6 +882,9 @@ static void showARM64VecBinOp(/*OUT*/const HChar** nm,
       case ARM64vecb_ORR:      *nm = "orr "; *ar = "all"; return;
       case ARM64vecb_XOR:      *nm = "eor "; *ar = "all"; return;
       case ARM64vecb_CMEQ64x2: *nm = "cmeq"; *ar = "2d";  return;
+      case ARM64vecb_CMEQ32x4: *nm = "cmeq"; *ar = "4s";  return;
+      case ARM64vecb_CMEQ16x8: *nm = "cmeq"; *ar = "8h";  return;
+      case ARM64vecb_CMEQ8x16: *nm = "cmeq"; *ar = "16b"; return;
       default: vpanic("showARM64VecBinOp");
    }
 }
@@ -4945,7 +4948,11 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
             010 01110 10 1 m  000111 n d   ORR Vd, Vn, Vm
             011 01110 00 1 m  000111 n d   EOR Vd, Vn, Vm
 
-            011 01110 11 1 m  100011 n d   CMEQ Vd.2d, Vn.2d, Vm.2d
+            011 01110 11 1 m  100011 n d   CMEQ Vd.2d,  Vn.2d,  Vm.2d
+            011 01110 10 1 m  100011 n d   CMEQ Vd.4s,  Vn.4s,  Vm.4s
+            011 01110 01 1 m  100011 n d   CMEQ Vd.8h,  Vn.8h,  Vm.8h
+            011 01110 00 1 m  100011 n d   CMEQ Vd.16b, Vn.16b, Vm.16b
+
             011 01110 11 1 m  001101 n d   CMHI Vd.2d, Vn.2d, Vm.2d  >u, ATC
             010 01110 11 1 m  001101 n d   CMGT Vd.2d, Vn.2d, Vm.2d  >s, ATC
          */
@@ -5055,6 +5062,15 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
             case ARM64vecb_CMEQ64x2:
                *p++ = X_3_8_5_6_5_5(X011, X01110111, vM, X100011, vN, vD);
                break;
+            case ARM64vecb_CMEQ32x4:
+               *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X100011, vN, vD);
+               break;
+            case ARM64vecb_CMEQ16x8:
+               *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X100011, vN, vD);
+               break;
+            case ARM64vecb_CMEQ8x16:
+               *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X100011, vN, vD);
+               break;
 
             default:
                goto bad;
diff --git a/VEX/priv/host_arm64_defs.h b/VEX/priv/host_arm64_defs.h
index a3531341fc..ede7e55ba4 100644
--- a/VEX/priv/host_arm64_defs.h
+++ b/VEX/priv/host_arm64_defs.h
@@ -339,6 +339,9 @@ typedef
       ARM64vecb_ORR,
       ARM64vecb_XOR,
       ARM64vecb_CMEQ64x2,
+      ARM64vecb_CMEQ32x4,
+      ARM64vecb_CMEQ16x8,
+      ARM64vecb_CMEQ8x16,
       ARM64vecb_INVALID
    }
    ARM64VecBinOp;
diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c
index 40978dd015..d50a6db640 100644
--- a/VEX/priv/host_arm64_isel.c
+++ b/VEX/priv/host_arm64_isel.c
@@ -4414,9 +4414,9 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
             addInstr(env, ARM64Instr_VUnaryV(op, res, arg));
             return res;
          }
-         //ATC case Iop_CmpNEZ8x16:
-         //ATC case Iop_CmpNEZ16x8:
-         //ATC case Iop_CmpNEZ32x4:
+         case Iop_CmpNEZ8x16:
+         case Iop_CmpNEZ16x8:
+         case Iop_CmpNEZ32x4:
          case Iop_CmpNEZ64x2: {
             HReg arg  = iselV128Expr(env, e->Iex.Unop.arg);
             HReg zero = newVRegV(env);
@@ -4424,6 +4424,9 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
             ARM64VecBinOp cmp = ARM64vecb_INVALID;
             switch (e->Iex.Unop.op) {
                case Iop_CmpNEZ64x2: cmp = ARM64vecb_CMEQ64x2; break;
+               case Iop_CmpNEZ32x4: cmp = ARM64vecb_CMEQ32x4; break;
+               case Iop_CmpNEZ16x8: cmp = ARM64vecb_CMEQ16x8; break;
+               case Iop_CmpNEZ8x16: cmp = ARM64vecb_CMEQ8x16; break;
                default: vassert(0);
             }
             // This is pretty feeble.  Better: use CMP against zero