From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 09:31:39 +0000 (+0200) Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 X-Git-Tag: v6.15-rc1~159^2~23^2~37 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=aadaa27956e3430217d9e6b8af5880e39b05b961;p=thirdparty%2Flinux.git arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI1 PHY. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner --- diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 8b2edf362ce84..ce890a3f39745 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -480,6 +480,7 @@ reg = <0x0 0xfed70000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,