From: Uros Bizjak Date: Thu, 28 Nov 2024 16:44:03 +0000 (+0100) Subject: i386: Macroize compound shift patterns some more X-Git-Tag: basepoints/gcc-16~3790 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ab2cce593ef6085a5f517cdca2520c5c44acbfad;p=thirdparty%2Fgcc.git i386: Macroize compound shift patterns some more Merge ashl and compound define_insn_and_split patterns to form macroized pattern. No functional changes. gcc/ChangeLog: * config/i386/i386.md (*3_mask): Macroize pattern from *ashl3_mask and *3_mask using any_shift code iterator. (*3_mask_1): Macroize pattern from *ashl3_mask_1 and *3_mask_1 using any_shift code iterator. (*3_add): Macroize pattern from *ashl3_add and *3_add using any_shift code iterator. (*3_add_1): Macroize pattern from *ashl3_add_1 and *3_add_1 using any_shift code iterator. (*3_sub): Macroize pattern from *ashl3_sub and *3_sub using any_shift code iterator. (*3_sub_1): Macroize pattern from *ashl3_sub_1 and *3_sub_1 using any_shift code iterator. --- diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2fc48006bca7..8eb9cb682b11 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15847,157 +15847,6 @@ DONE; }) -;; Avoid useless masking of count operand. -(define_insn_and_split "*ashl3_mask" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (ashift:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (subreg:QI - (and - (match_operand 2 "int248_register_operand" "c,r") - (match_operand 3 "const_int_operand")) 0))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFT, mode, operands) - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) - == GET_MODE_BITSIZE (mode)-1 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (ashift:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] -{ - operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); - operands[2] = gen_lowpart (QImode, operands[2]); -} - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*ashl3_mask_1" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (ashift:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (and:QI - (match_operand:QI 2 "register_operand" "c,r") - (match_operand:QI 3 "const_int_operand")))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFT, mode, operands) - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) - == GET_MODE_BITSIZE (mode)-1 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (ashift:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] - "" - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*ashl3_add" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (ashift:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (subreg:QI - (plus - (match_operand 2 "int248_register_operand" "c,r") - (match_operand 3 "const_int_operand")) 0))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFT, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (ashift:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] -{ - operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); - operands[2] = gen_lowpart (QImode, operands[2]); -} - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*ashl3_add_1" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (ashift:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (plus:QI - (match_operand:QI 2 "register_operand" "c,r") - (match_operand:QI 3 "const_int_operand")))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFT, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (ashift:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] - "" - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*ashl3_sub" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (ashift:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (subreg:QI - (minus - (match_operand 3 "const_int_operand") - (match_operand 2 "int248_register_operand" "c,r")) 0))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFT, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 4) - (neg:QI (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (parallel - [(set (match_dup 0) - (ashift:SWI48 (match_dup 1) - (match_dup 4))) - (clobber (reg:CC FLAGS_REG))])] -{ - operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); - operands[2] = gen_lowpart (QImode, operands[2]); - - operands[4] = gen_reg_rtx (QImode); -} - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*ashl3_sub_1" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (ashift:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (minus:QI - (match_operand:QI 3 "const_int_operand") - (match_operand:QI 2 "register_operand" "c,r")))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (ASHIFT, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 4) - (neg:QI (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (parallel - [(set (match_dup 0) - (ashift:SWI48 (match_dup 1) - (match_dup 4))) - (clobber (reg:CC FLAGS_REG))])] - "operands[4] = gen_reg_rtx (QImode);" - [(set_attr "isa" "*,bmi2")]) - (define_insn "*bmi2_ashl3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") @@ -16675,157 +16524,6 @@ DONE; }) -;; Avoid useless masking of count operand. -(define_insn_and_split "*3_mask" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (any_shiftrt:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (subreg:QI - (and - (match_operand 2 "int248_register_operand" "c,r") - (match_operand 3 "const_int_operand")) 0))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (, mode, operands) - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) - == GET_MODE_BITSIZE (mode)-1 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (any_shiftrt:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] -{ - operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); - operands[2] = gen_lowpart (QImode, operands[2]); -} - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*3_mask_1" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (any_shiftrt:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (and:QI - (match_operand:QI 2 "register_operand" "c,r") - (match_operand:QI 3 "const_int_operand")))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (, mode, operands) - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) - == GET_MODE_BITSIZE (mode)-1 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (any_shiftrt:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] - "" - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*3_add" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (any_shiftrt:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (subreg:QI - (plus - (match_operand 2 "int248_register_operand" "c,r") - (match_operand 3 "const_int_operand")) 0))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (any_shiftrt:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] -{ - operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); - operands[2] = gen_lowpart (QImode, operands[2]); -} - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*3_add_1" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (any_shiftrt:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (plus:QI - (match_operand:QI 2 "register_operand" "c,r") - (match_operand:QI 3 "const_int_operand")))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 0) - (any_shiftrt:SWI48 (match_dup 1) - (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])] - "" - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*3_sub" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (any_shiftrt:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (subreg:QI - (minus - (match_operand 3 "const_int_operand") - (match_operand 2 "int248_register_operand" "c,r")) 0))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 4) - (neg:QI (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (parallel - [(set (match_dup 0) - (any_shiftrt:SWI48 (match_dup 1) - (match_dup 4))) - (clobber (reg:CC FLAGS_REG))])] -{ - operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); - operands[2] = gen_lowpart (QImode, operands[2]); - - operands[4] = gen_reg_rtx (QImode); -} - [(set_attr "isa" "*,bmi2")]) - -(define_insn_and_split "*3_sub_1" - [(set (match_operand:SWI48 0 "nonimmediate_operand") - (any_shiftrt:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand") - (minus:QI - (match_operand:QI 3 "const_int_operand") - (match_operand:QI 2 "register_operand" "c,r")))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (, mode, operands) - && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(parallel - [(set (match_dup 4) - (neg:QI (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (parallel - [(set (match_dup 0) - (any_shiftrt:SWI48 (match_dup 1) - (match_dup 4))) - (clobber (reg:CC FLAGS_REG))])] - "operands[4] = gen_reg_rtx (QImode);" - [(set_attr "isa" "*,bmi2")]) - (define_insn_and_split "*3_doubleword_mask" [(set (match_operand: 0 "register_operand") (any_shiftrt: @@ -18093,6 +17791,157 @@ (const_string "*"))) (set_attr "mode" "QI")]) +;; Avoid useless masking of count operand. +(define_insn_and_split "*3_mask" + [(set (match_operand:SWI48 0 "nonimmediate_operand") + (any_shift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand") + (subreg:QI + (and + (match_operand 2 "int248_register_operand" "c,r") + (match_operand 3 "const_int_operand")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) + == * BITS_PER_UNIT - 1 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 0) + (any_shift:SWI48 (match_dup 1) + (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] +{ + operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); + operands[2] = gen_lowpart (QImode, operands[2]); +} + [(set_attr "isa" "*,bmi2")]) + +(define_insn_and_split "*3_mask_1" + [(set (match_operand:SWI48 0 "nonimmediate_operand") + (any_shift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand") + (and:QI + (match_operand:QI 2 "register_operand" "c,r") + (match_operand:QI 3 "const_int_operand")))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) + == * BITS_PER_UNIT - 1 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 0) + (any_shift:SWI48 (match_dup 1) + (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "isa" "*,bmi2")]) + +(define_insn_and_split "*3_add" + [(set (match_operand:SWI48 0 "nonimmediate_operand") + (any_shift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand") + (subreg:QI + (plus + (match_operand 2 "int248_register_operand" "c,r") + (match_operand 3 "const_int_operand")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 0) + (any_shift:SWI48 (match_dup 1) + (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] +{ + operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); + operands[2] = gen_lowpart (QImode, operands[2]); +} + [(set_attr "isa" "*,bmi2")]) + +(define_insn_and_split "*3_add_1" + [(set (match_operand:SWI48 0 "nonimmediate_operand") + (any_shift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand") + (plus:QI + (match_operand:QI 2 "register_operand" "c,r") + (match_operand:QI 3 "const_int_operand")))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 0) + (any_shift:SWI48 (match_dup 1) + (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "isa" "*,bmi2")]) + +(define_insn_and_split "*3_sub" + [(set (match_operand:SWI48 0 "nonimmediate_operand") + (any_shift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand") + (subreg:QI + (minus + (match_operand 3 "const_int_operand") + (match_operand 2 "int248_register_operand" "c,r")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 4) + (neg:QI (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel + [(set (match_dup 0) + (any_shift:SWI48 (match_dup 1) + (match_dup 4))) + (clobber (reg:CC FLAGS_REG))])] +{ + operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); + operands[2] = gen_lowpart (QImode, operands[2]); + + operands[4] = gen_reg_rtx (QImode); +} + [(set_attr "isa" "*,bmi2")]) + +(define_insn_and_split "*3_sub_1" + [(set (match_operand:SWI48 0 "nonimmediate_operand") + (any_shift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand") + (minus:QI + (match_operand:QI 3 "const_int_operand") + (match_operand:QI 2 "register_operand" "c,r")))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & ( * BITS_PER_UNIT - 1)) == 0 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 4) + (neg:QI (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel + [(set (match_dup 0) + (any_shift:SWI48 (match_dup 1) + (match_dup 4))) + (clobber (reg:CC FLAGS_REG))])] + "operands[4] = gen_reg_rtx (QImode);" + [(set_attr "isa" "*,bmi2")]) + (define_insn_and_split "*extend2_doubleword_highpart" [(set (match_operand: 0 "register_operand" "=r") (ashiftrt: