From: Aleksandar Markovic <amarkovic@wavecomp.com>
Date: Mon, 15 Jul 2019 20:00:44 +0000 (+0200)
Subject: target/mips: Add missing 'break' for a case of MTHC0 handling
X-Git-Tag: v4.1.0-rc1~5^2~2
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ab8c34105a0ddd0c05159fb76919a18de8df4e8f;p=thirdparty%2Fqemu.git

target/mips: Add missing 'break' for a case of MTHC0 handling

This was found by GCC 8.3 static analysis.

Fixes: 5fb2dcd1792

Reported-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1563220847-14630-3-git-send-email-aleksandar.markovic@rt-rk.com>
---

diff --git a/target/mips/translate.c b/target/mips/translate.c
index f96f141cdf2..cce1f125900 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6745,6 +6745,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         default:
             goto cp0_unimplemented;
         }
+        break;
     case CP0_REGISTER_17:
         switch (sel) {
         case 0: