From: Fabiano Rosas Date: Fri, 18 Feb 2022 07:34:14 +0000 (+0100) Subject: target/ppc: cpu_init: Move 405 SPRs into register_405_sprs X-Git-Tag: v7.0.0-rc0~48^2~21 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=acd1f78870aca0b7f9e54d788b9bc3d36f80f01d;p=thirdparty%2Fqemu.git target/ppc: cpu_init: Move 405 SPRs into register_405_sprs Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220216162426.1885923-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 53409a176ac..c0990b43a2b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1425,6 +1425,18 @@ static void register_405_sprs(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, spr_read_generic, &spr_write_generic, 0x00000000); + + /* Bus access control */ + /* not emulated, as QEMU never does speculative access */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); } @@ -2316,17 +2328,7 @@ static void init_proc_405(CPUPPCState *env) register_40x_sprs(env); register_405_sprs(env); register_usprgh_sprs(env); - /* Bus access control */ - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); + /* Memory management */ #if !defined(CONFIG_USER_ONLY) env->nb_tlb = 64;