From: Kruti <kpendharkar@vmware.com>
Date: Mon, 18 Mar 2024 18:03:49 +0000 (-0700)
Subject: Change to common header file not applicable to open-vm-tools.
X-Git-Tag: stable-12.5.0~116
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=acfd8ab650f10759b09a93f8adde71459a131392;p=thirdparty%2Fopen-vm-tools.git

Change to common header file not applicable to open-vm-tools.
---

diff --git a/open-vm-tools/lib/include/vm_basic_asm_arm64.h b/open-vm-tools/lib/include/vm_basic_asm_arm64.h
index 88faddbfb..18908ba2c 100644
--- a/open-vm-tools/lib/include/vm_basic_asm_arm64.h
+++ b/open-vm-tools/lib/include/vm_basic_asm_arm64.h
@@ -244,7 +244,18 @@ ESB(void)
  * Thanks for pasting this whole comment into every architecture header.
  */
 
-#define COMPILER_MEM_BARRIER()   SMP_RW_BARRIER_RW()
+/*
+ * To match x86 TSO semantics, we need to guarantee ordering for
+ * everything _except_ store-load:
+ *
+ * - DMB ISHLD orders load-load and load-store.
+ * - DMB ISHST orders store-store.
+ *
+ * In contrast, SMP_RW_BARRIER_RW, or DMB ISH, orders all four
+ * (load-load, load-store, store-load, store-store), so it's stronger
+ * than we need -- like x86 MFENCE.
+ */
+#define COMPILER_MEM_BARRIER() do { _DMB(ISHLD); _DMB(ISHST); } while (0)
 
 /*
  * Memory barriers. These take the form of