From: Joerg Roedel <joerg.roedel@amd.com>
Date: Fri, 6 Feb 2026 10:10:40 +0000 (+0100)
Subject: Merge branches 'fixes', 'arm/smmu/updates', 'intel/vt-d', 'amd/amd-vi' and 'core... 
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ad095636604604b3574c1920260b1360c25ced6f;p=thirdparty%2Fkernel%2Flinux.git

Merge branches 'fixes', 'arm/smmu/updates', 'intel/vt-d', 'amd/amd-vi' and 'core' into next
---

ad095636604604b3574c1920260b1360c25ced6f
diff --cc drivers/iommu/amd/iommu.c
index 7c12be1b247f4,9f1d56a5e145f,5d45795c367a6,58be841d624e5,5d45795c367a6..f5cbcc77824ee
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@@@@@ -2022,30 -2013,30 -2022,30 -2078,24 -2022,30 +2078,24 @@@@@@ int amd_iommu_clear_gcr3(struct iommu_d
      * Note:
      * The old value for GCR3 table and GPT have been cleared from caller.
      */
--- -static void set_dte_gcr3_table(struct amd_iommu *iommu,
--- -			       struct iommu_dev_data *dev_data,
--- -			       struct dev_table_entry *target)
+++ +static void set_dte_gcr3_table(struct iommu_dev_data *dev_data,
+++ +			       struct dev_table_entry *new)
     {
     	struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
--- -	u64 gcr3;
--- -
--- -	if (!gcr3_info->gcr3_tbl)
--- -		return;
-    
-    	pr_debug("%s: devid=%#x, glx=%#x, gcr3_tbl=%#llx\n",
-    		 __func__, dev_data->devid, gcr3_info->glx,
-    		 (unsigned long long)gcr3_info->gcr3_tbl);
+++ +	u64 gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl);
     
-    	gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl);
 -- -	pr_debug("%s: devid=%#x, glx=%#x, gcr3_tbl=%#llx\n",
 -- -		 __func__, dev_data->devid, gcr3_info->glx,
 -- -		 (unsigned long long)gcr3_info->gcr3_tbl);
+++ +	new->data[0] |= DTE_FLAG_TV |
+++ +			(dev_data->ppr ? DTE_FLAG_PPR : 0) |
+++ +			(pdom_is_v2_pgtbl_mode(dev_data->domain) ?  DTE_FLAG_GIOV : 0) |
+++ +			DTE_FLAG_GV |
+++ +			FIELD_PREP(DTE_GLX, gcr3_info->glx) |
+++ +			FIELD_PREP(DTE_GCR3_14_12, gcr3 >> 12) |
+++ +			DTE_FLAG_IR | DTE_FLAG_IW;
     
 -- -	gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl);
 -- -
--- -	target->data[0] |= DTE_FLAG_GV |
--- -			   FIELD_PREP(DTE_GLX, gcr3_info->glx) |
--- -			   FIELD_PREP(DTE_GCR3_14_12, gcr3 >> 12);
--- -	if (pdom_is_v2_pgtbl_mode(dev_data->domain))
--- -		target->data[0] |= DTE_FLAG_GIOV;
--- -
--- -	target->data[1] |= FIELD_PREP(DTE_GCR3_30_15, gcr3 >> 15) |
--- -			   FIELD_PREP(DTE_GCR3_51_31, gcr3 >> 31);
+++ +	new->data[1] |= FIELD_PREP(DTE_DOMID_MASK, dev_data->gcr3_info.domid) |
+++ +			FIELD_PREP(DTE_GCR3_30_15, gcr3 >> 15) |
+++ +			(dev_data->ats_enabled ? DTE_FLAG_IOTLB : 0) |
+++ +			FIELD_PREP(DTE_GCR3_51_31, gcr3 >> 31);
     
     	/* Guest page table can only support 4 and 5 levels  */
     	if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL)
@@@@@@ -2774,9 -2766,9 -2775,9 -2829,20 -2775,9 +2828,20 @@@@@@ amd_iommu_domain_alloc_paging_flags(str
     
     	switch (flags & supported_flags) {
     	case IOMMU_HWPT_ALLOC_DIRTY_TRACKING:
--- -		/* Allocate domain with v1 page table for dirty tracking */
--- -		if (!amd_iommu_hd_support(iommu))
+++ +	case IOMMU_HWPT_ALLOC_NEST_PARENT:
+++ +	case IOMMU_HWPT_ALLOC_DIRTY_TRACKING | IOMMU_HWPT_ALLOC_NEST_PARENT:
+++ +		/*
+++ +		 * Allocate domain with v1 page table for dirty tracking
+++ +		 * and/or Nest parent.
+++ +		 */
+++ +		if ((flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING) &&
+++ +		    !amd_iommu_hd_support(iommu))
 ++ +			break;
+++ +
+++ +		if ((flags & IOMMU_HWPT_ALLOC_NEST_PARENT) &&
+++ +		    !is_nest_parent_supported(flags))
+    			break;
+++ +
     		return amd_iommu_domain_alloc_paging_v1(dev, flags);
     	case IOMMU_HWPT_ALLOC_PASID:
     		/* Allocate domain with v2 page table if IOMMU supports PASID. */