From: Richard Henderson Date: Thu, 25 Jun 2026 01:51:50 +0000 (-0700) Subject: target/arm: Rename SME FMLAL/FMLSL patterns X-Git-Tag: v11.1.0-rc0~36^2~9 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ad31eebc5a4eaeba886a0a2a7fb8565cc55a33a3;p=thirdparty%2Fqemu.git target/arm: Rename SME FMLAL/FMLSL patterns Rename patterns to include _sh suffix, so that we can distinguish insns of the same name from FEAT_SME_F8F16. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 1de5f341ef..90ee161461 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -324,13 +324,13 @@ SUB_azz_n1_d 11000001 0111 .... 0 .. 110 ..... 11 ... @azz_nx1_o3 n=4 @azz_nx1_o2x2 ........ ... . zm:4 . .. ... zn:5 ... .. \ &azz_n off=%off2_x2 rv=%mova_rv -FMLAL_n1 11000001 001 0 .... 0 .. 011 ..... 00 ... @azz_nx1_o3x2 n=1 -FMLAL_n1 11000001 001 0 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 n=2 -FMLAL_n1 11000001 001 1 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 n=4 +FMLAL_n1_sh 11000001 001 0 .... 0 .. 011 ..... 00 ... @azz_nx1_o3x2 n=1 +FMLAL_n1_sh 11000001 001 0 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 n=2 +FMLAL_n1_sh 11000001 001 1 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 n=4 -FMLSL_n1 11000001 001 0 .... 0 .. 011 ..... 01 ... @azz_nx1_o3x2 n=1 -FMLSL_n1 11000001 001 0 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 n=2 -FMLSL_n1 11000001 001 1 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 n=4 +FMLSL_n1_sh 11000001 001 0 .... 0 .. 011 ..... 01 ... @azz_nx1_o3x2 n=1 +FMLSL_n1_sh 11000001 001 0 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 n=2 +FMLSL_n1_sh 11000001 001 1 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 n=4 BFMLAL_n1 11000001 001 0 .... 0 .. 011 ..... 10 ... @azz_nx1_o3x2 n=1 BFMLAL_n1 11000001 001 0 .... 0 .. 010 ..... 100 .. @azz_nx1_o2x2 n=2 @@ -477,11 +477,11 @@ SUB_azz_nn_d 11000001 111 ...01 0 .. 110 ...00 11 ... @azz_4x4_o3 @azz_4x4_o2x2 ........ ... ..... . .. ... ..... ... .. \ &azz_n n=4 rv=%mova_rv zn=%zn_ax4 zm=%zm_ax4 off=%off2_x2 -FMLAL_nn 11000001 101 ....0 0 .. 010 ....0 000 .. @azz_2x2_o2x2 -FMLAL_nn 11000001 101 ...01 0 .. 010 ...00 000 .. @azz_4x4_o2x2 +FMLAL_nn_sh 11000001 101 ....0 0 .. 010 ....0 000 .. @azz_2x2_o2x2 +FMLAL_nn_sh 11000001 101 ...01 0 .. 010 ...00 000 .. @azz_4x4_o2x2 -FMLSL_nn 11000001 101 ....0 0 .. 010 ....0 010 .. @azz_2x2_o2x2 -FMLSL_nn 11000001 101 ...01 0 .. 010 ...00 010 .. @azz_4x4_o2x2 +FMLSL_nn_sh 11000001 101 ....0 0 .. 010 ....0 010 .. @azz_2x2_o2x2 +FMLSL_nn_sh 11000001 101 ...01 0 .. 010 ...00 010 .. @azz_4x4_o2x2 BFMLAL_nn 11000001 101 ....0 0 .. 010 ....0 100 .. @azz_2x2_o2x2 BFMLAL_nn 11000001 101 ...01 0 .. 010 ...00 100 .. @azz_4x4_o2x2 @@ -617,13 +617,13 @@ BFSUB_nn 11000001 111 00101 0 .. 111 ...00 01 ... @az_4x4_o3 @azx_4x1_o2x2 ........ .... zm:4 . .. . .. ..... .. ... \ &azx_n n=4 rv=%mova_rv off=%off2_x2 zn=%zn_ax4 idx=%idx2_10_2 -FMLAL_nx 11000001 1000 .... . .. 1 .. ..... 00 ... @azx_1x1_o3x2 -FMLAL_nx 11000001 1001 .... 0 .. 1 .. ....0 00 ... @azx_2x1_o2x2 -FMLAL_nx 11000001 1001 .... 1 .. 1 .. ...00 00 ... @azx_4x1_o2x2 +FMLAL_nx_sh 11000001 1000 .... . .. 1 .. ..... 00 ... @azx_1x1_o3x2 +FMLAL_nx_sh 11000001 1001 .... 0 .. 1 .. ....0 00 ... @azx_2x1_o2x2 +FMLAL_nx_sh 11000001 1001 .... 1 .. 1 .. ...00 00 ... @azx_4x1_o2x2 -FMLSL_nx 11000001 1000 .... . .. 1 .. ..... 01 ... @azx_1x1_o3x2 -FMLSL_nx 11000001 1001 .... 0 .. 1 .. ....0 01 ... @azx_2x1_o2x2 -FMLSL_nx 11000001 1001 .... 1 .. 1 .. ...00 01 ... @azx_4x1_o2x2 +FMLSL_nx_sh 11000001 1000 .... . .. 1 .. ..... 01 ... @azx_1x1_o3x2 +FMLSL_nx_sh 11000001 1001 .... 0 .. 1 .. ....0 01 ... @azx_2x1_o2x2 +FMLSL_nx_sh 11000001 1001 .... 1 .. 1 .. ...00 01 ... @azx_4x1_o2x2 BFMLAL_nx 11000001 1000 .... . .. 1 .. ..... 10 ... @azx_1x1_o3x2 BFMLAL_nx 11000001 1001 .... 0 .. 1 .. ....0 10 ... @azx_2x1_o2x2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index b8dde80c20..7aa270d3ec 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1107,10 +1107,10 @@ static bool do_fmlal(DisasContext *s, arg_azz_n *a, bool sub, bool multi) multi, FPST_ENV, gen_helper_sve2_fmlal_zzzw_s); } -TRANS_FEAT(FMLAL_n1, aa64_sme2, do_fmlal, a, false, false) -TRANS_FEAT(FMLSL_n1, aa64_sme2, do_fmlal, a, true, false) -TRANS_FEAT(FMLAL_nn, aa64_sme2, do_fmlal, a, false, true) -TRANS_FEAT(FMLSL_nn, aa64_sme2, do_fmlal, a, true, true) +TRANS_FEAT(FMLAL_n1_sh, aa64_sme2, do_fmlal, a, false, false) +TRANS_FEAT(FMLSL_n1_sh, aa64_sme2, do_fmlal, a, true, false) +TRANS_FEAT(FMLAL_nn_sh, aa64_sme2, do_fmlal, a, false, true) +TRANS_FEAT(FMLSL_nn_sh, aa64_sme2, do_fmlal, a, true, true) static bool do_fmlall_fp8(DisasContext *s, arg_azz_n *a, bool multi) { @@ -1128,8 +1128,8 @@ static bool do_fmlal_nx(DisasContext *s, arg_azx_n *a, bool sub) false, FPST_ENV, gen_helper_sve2_fmlal_zzxw_s); } -TRANS_FEAT(FMLAL_nx, aa64_sme2, do_fmlal_nx, a, false) -TRANS_FEAT(FMLSL_nx, aa64_sme2, do_fmlal_nx, a, true) +TRANS_FEAT(FMLAL_nx_sh, aa64_sme2, do_fmlal_nx, a, false) +TRANS_FEAT(FMLSL_nx_sh, aa64_sme2, do_fmlal_nx, a, true) static bool do_bfmlal(DisasContext *s, arg_azz_n *a, bool sub, bool multi) {