From: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Date: Tue, 25 Jan 2011 07:18:05 +0000 (+0000)
Subject: backport: re PR target/44392 (libgcc compile with --enable-target-optspace (-Os)... 
X-Git-Tag: releases/gcc-4.5.3~277
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ad4d9710cd7ed432a322f31141a418efc98e2278;p=thirdparty%2Fgcc.git

backport: re PR target/44392 (libgcc compile with --enable-target-optspace (-Os) causes recursion in __bswapsi2)

2011-01-21  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	Backport from mainline.
	2010-09-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/44392
	* config/arm/arm.md (bswapsi2): Handle condition correctly
	for armv6 and optimize_size.

From-SVN: r169221
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3ba8544c3890..45586f4ddea9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2011-01-21  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	Backport from mainline.
+	2010-09-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	PR target/44392
+	* config/arm/arm.md (bswapsi2): Handle condition correctly
+	for armv6 and optimize_size.
+
 2011-01-21  Richard Guenther  <rguenther@suse.de>
 
 	PR tree-optimization/47365
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 482f8a7aa489..0de4a1441d5a 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -11273,34 +11273,29 @@
 (define_expand "bswapsi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
   	(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
-"TARGET_EITHER"
+"TARGET_EITHER && (arm_arch6 || !optimize_size)"
 "
-  if (!arm_arch6)
-    {
-      if (!optimize_size)
-	{
-	  rtx op2 = gen_reg_rtx (SImode);
-	  rtx op3 = gen_reg_rtx (SImode);
+    if (!arm_arch6)
+      {
+	rtx op2 = gen_reg_rtx (SImode);
+	rtx op3 = gen_reg_rtx (SImode);
 
-	  if (TARGET_THUMB)
-	    {
-	      rtx op4 = gen_reg_rtx (SImode);
-	      rtx op5 = gen_reg_rtx (SImode);
+	if (TARGET_THUMB)
+	  {
+	    rtx op4 = gen_reg_rtx (SImode);
+	    rtx op5 = gen_reg_rtx (SImode);
 
-	      emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
-					       op2, op3, op4, op5));
-	    }
-	  else
-	    {
-	      emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
-					     op2, op3));
-	    }
+	    emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
+					     op2, op3, op4, op5));
+	  }
+	else
+	  {
+	    emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
+					   op2, op3));
+	  }
 
-	  DONE;
-	}
-      else
-	FAIL;
-    }
+	DONE;
+      }
   "
 )