From: Shuming Fan Date: Fri, 27 Mar 2026 08:23:31 +0000 (+0800) Subject: ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ae00200acb870ac00551350f26f03ced188bad6f;p=thirdparty%2Flinux.git ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format The division calculation should be implemented using signed integer format. This patch changes mc->shift from an unsigned type to a signed integer during the calculation. Fixes: 501efdcb3b3a ("ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops") Signed-off-by: Shuming Fan Reviewed-by: Charles Keepax Link: https://patch.msgid.link/20260327082331.2277498-1-shumingf@realtek.com Signed-off-by: Mark Brown --- diff --git a/sound/soc/sdca/sdca_asoc.c b/sound/soc/sdca/sdca_asoc.c index 733c9808891a4..7709a4ce26e09 100644 --- a/sound/soc/sdca/sdca_asoc.c +++ b/sound/soc/sdca/sdca_asoc.c @@ -850,7 +850,7 @@ static int q78_read(struct snd_soc_component *component, reg_val = snd_soc_component_read(component, reg); - val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min; + val = (sign_extend32(reg_val, mc->sign_bit) / (int)mc->shift) - mc->min; return val & GENMASK(mc->sign_bit, 0); }