From: Peter Bergner Date: Thu, 13 Jun 2024 02:05:34 +0000 (-0500) Subject: rs6000: Fix pr66144-3.c test to accept multiple equivalent insns. [PR115262] X-Git-Tag: basepoints/gcc-16~8321 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ae8103a3a13ac412b9ca33222594cb507ceac9f7;p=thirdparty%2Fgcc.git rs6000: Fix pr66144-3.c test to accept multiple equivalent insns. [PR115262] Jeff's commit r15-831-g05daf617ea22e1 changed the instruction we expected for this test case into an equivalent instruction. Modify the test case so it will accept any of three instructions we could get depending on the options used. 2024-06-12 Peter Bergner gcc/testsuite/ PR testsuite/115262 * gcc.target/powerpc/pr66144-3.c (dg-do): Compile for all targets. (dg-options): Add -fno-unroll-loops and remove -mvsx. (scan-assembler): Change from this... (scan-assembler-times): ...to this. Tweak regex to accept multiple allowable instructions. --- diff --git a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c index 4c93b2a7a3d..14ecb809edc 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { powerpc64*-*-* } } } */ -/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize" } */ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fno-unroll-loops" } */ /* { dg-require-effective-target powerpc_vsx } */ /* Verify that we can optimize a vector conditional move, where one of the arms @@ -20,7 +20,7 @@ test (void) a[i] = (b[i] == c[i]) ? -1 : a[i]; } -/* { dg-final { scan-assembler {\mvcmpequw\M} } } */ -/* { dg-final { scan-assembler {\mxxsel\M} } } */ +/* { dg-final { scan-assembler-times {\mvcmpequw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\m(?:xxsel|xxlor|vor)\M} 1 } } */ /* { dg-final { scan-assembler-not {\mvspltisw\M} } } */ /* { dg-final { scan-assembler-not {\mxxlorc\M} } } */