From: Christophe Lyon Date: Thu, 8 Sep 2022 13:31:24 +0000 (+0000) Subject: arm: [MVE intrinsics] factorize vadd vsubq vmulq X-Git-Tag: basepoints/gcc-15~9700 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b0b3a5e914727a9ec964be12ca4849a51b1e3dcf;p=thirdparty%2Fgcc.git arm: [MVE intrinsics] factorize vadd vsubq vmulq In order to avoid using a huge switch when generating all the intrinsics (e.g. mve_vaddq_n_sv4si, ...), we want to generate a single function taking the builtin code as parameter (e.g. mve_q_n (VADDQ_S, ....) This is achieved by using the new mve_insn iterator. Having done that, it becomes easier to share similar patterns, to avoid useless/error-prone code duplication. 2022-09-08 Christophe Lyon gcc/ChangeLog: * config/arm/iterators.md (MVE_INT_BINARY_RTX, MVE_INT_M_BINARY) (MVE_INT_M_N_BINARY, MVE_INT_N_BINARY, MVE_FP_M_BINARY) (MVE_FP_M_N_BINARY, MVE_FP_N_BINARY, mve_addsubmul, mve_insn): New iterators. * config/arm/mve.md (mve_vsubq_n_f, mve_vaddq_n_f, mve_vmulq_n_f): Factorize into ... (@mve_q_n_f): ... this. (mve_vaddq_n_, mve_vmulq_n_) (mve_vsubq_n_): Factorize into ... (@mve_q_n_): ... this. (mve_vaddq, mve_vmulq, mve_vsubq): Factorize into ... (mve_q): ... this. (mve_vaddq_f, mve_vmulq_f, mve_vsubq_f): Factorize into ... (mve_q_f): ... this. (mve_vaddq_m_, mve_vmulq_m_) (mve_vsubq_m_): Factorize into ... (@mve_q_m_): ... this, (mve_vaddq_m_n_, mve_vmulq_m_n_) (mve_vsubq_m_n_): Factorize into ... (@mve_q_m_n_): ... this. (mve_vaddq_m_f, mve_vmulq_m_f, mve_vsubq_m_f): Factorize into ... (@mve_q_m_f): ... this. (mve_vaddq_m_n_f, mve_vmulq_m_n_f) (mve_vsubq_m_n_f): Factorize into ... (@mve_q_m_n_f): ... this. --- diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 39895ad62aa3..d3bef594775e 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -330,6 +330,63 @@ ;; Saturating addition, subtraction (define_code_iterator SSPLUSMINUS [ss_plus ss_minus]) +;; MVE integer binary operations. +(define_code_iterator MVE_INT_BINARY_RTX [plus minus mult]) + +(define_int_iterator MVE_INT_M_BINARY [ + VADDQ_M_S VADDQ_M_U + VMULQ_M_S VMULQ_M_U + VSUBQ_M_S VSUBQ_M_U + ]) + +(define_int_iterator MVE_INT_M_N_BINARY [ + VADDQ_M_N_S VADDQ_M_N_U + VMULQ_M_N_S VMULQ_M_N_U + VSUBQ_M_N_S VSUBQ_M_N_U + ]) + +(define_int_iterator MVE_INT_N_BINARY [ + VADDQ_N_S VADDQ_N_U + VMULQ_N_S VMULQ_N_U + VSUBQ_N_S VSUBQ_N_U + ]) + +(define_int_iterator MVE_FP_M_BINARY [ + VADDQ_M_F + VMULQ_M_F + VSUBQ_M_F + ]) + +(define_int_iterator MVE_FP_M_N_BINARY [ + VADDQ_M_N_F + VMULQ_M_N_F + VSUBQ_M_N_F + ]) + +(define_int_iterator MVE_FP_N_BINARY [ + VADDQ_N_F + VMULQ_N_F + VSUBQ_N_F + ]) + +(define_code_attr mve_addsubmul [ + (minus "vsub") + (mult "vmul") + (plus "vadd") + ]) + +(define_int_attr mve_insn [ + (VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd") + (VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd") + (VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd") + (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul") + (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul") + (VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F "vmul") + (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub") + (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub") + (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub") + ]) + ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows ;; a stack pointer operand. The minus operation is a candidate for an rsub ;; and hence only plus is supported. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index ab688396f978..90c38709acaa 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -668,21 +668,6 @@ [(set_attr "type" "mve_move") ]) -;; -;; [vsubq_n_f]) -;; -(define_insn "mve_vsubq_n_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VSUBQ_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vsub.f\t%q0, %q1, %2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vbrsrq_n_f]) ;; @@ -870,17 +855,19 @@ ]) ;; -;; [vaddq_n_s, vaddq_n_u]) +;; [vaddq_n_s, vaddq_n_u] +;; [vsubq_n_s, vsubq_n_u] +;; [vmulq_n_s, vmulq_n_u] ;; -(define_insn "mve_vaddq_n_" +(define_insn "@mve_q_n_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand: 2 "s_register_operand" "r")] - VADDQ_N)) + MVE_INT_N_BINARY)) ] "TARGET_HAVE_MVE" - "vadd.i%#\t%q0, %q1, %2" + ".i%#\t%q0, %q1, %2" [(set_attr "type" "mve_move") ]) @@ -1362,26 +1349,13 @@ ]) ;; -;; [vmulq_n_u, vmulq_n_s]) -;; -(define_insn "mve_vmulq_n_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VMULQ_N)) - ] - "TARGET_HAVE_MVE" - "vmul.i%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vmulq_u, vmulq_s]) +;; [vaddq_s, vaddq_u] +;; [vmulq_u, vmulq_s] +;; [vsubq_s, vsubq_u] ;; (define_insn "mve_vmulq_" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] VMULQ)) @@ -1391,14 +1365,14 @@ [(set_attr "type" "mve_move") ]) -(define_insn "mve_vmulq" +(define_insn "mve_q" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (mult:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w"))) + (MVE_INT_BINARY_RTX:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vmul.i%#\t%q0, %q1, %q2" + ".i%#\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) @@ -1768,21 +1742,6 @@ [(set_attr "type" "mve_move") ]) -;; -;; [vsubq_n_s, vsubq_n_u]) -;; -(define_insn "mve_vsubq_n_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VSUBQ_N)) - ] - "TARGET_HAVE_MVE" - "vsub.i%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vsubq_s, vsubq_u]) ;; @@ -1798,17 +1757,6 @@ [(set_attr "type" "mve_move") ]) -(define_insn "mve_vsubq" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (minus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w"))) - ] - "TARGET_HAVE_MVE" - "vsub.i%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vabdq_f]) ;; @@ -1840,17 +1788,19 @@ ]) ;; -;; [vaddq_n_f]) +;; [vaddq_n_f] +;; [vsubq_n_f] +;; [vmulq_n_f] ;; -(define_insn "mve_vaddq_n_f" +(define_insn "@mve_q_n_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand: 2 "s_register_operand" "r")] - VADDQ_N_F)) + MVE_FP_N_BINARY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vadd.f%#\t%q0, %q1, %2" + ".f%#\t%q0, %q1, %2" [(set_attr "type" "mve_move") ]) @@ -2224,31 +2174,18 @@ ]) ;; -;; [vmulq_f]) +;; [vaddq_f] +;; [vmulq_f] +;; [vsubq_f] ;; -(define_insn "mve_vmulq_f" +(define_insn "mve_q_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (mult:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (MVE_INT_BINARY_RTX:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vmul.f%# %q0, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vmulq_n_f]) -;; -(define_insn "mve_vmulq_n_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VMULQ_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vmul.f%# %q0, %q1, %2" + ".f%#\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) @@ -2490,20 +2427,6 @@ [(set_attr "type" "mve_move") ]) -;; -;; [vsubq_f]) -;; -(define_insn "mve_vsubq_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (minus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w"))) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vsub.f%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vmulltq_poly_p]) ;; @@ -5032,23 +4955,6 @@ [(set_attr "type" "mve_move") (set_attr "length" "8")]) -;; -;; [vsubq_m_u, vsubq_m_s]) -;; -(define_insn "mve_vsubq_m_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VSUBQ_M)) - ] - "TARGET_HAVE_MVE" - "vpst\;vsubt.i%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") - (set_attr "length" "8")]) - ;; ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) ;; @@ -5083,36 +4989,40 @@ (set_attr "length""8")]) ;; -;; [vaddq_m_n_s, vaddq_m_n_u]) +;; [vaddq_m_n_s, vaddq_m_n_u] +;; [vsubq_m_n_s, vsubq_m_n_u] +;; [vmulq_m_n_s, vmulq_m_n_u] ;; -(define_insn "mve_vaddq_m_n_" +(define_insn "@mve_q_m_n_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand: 3 "s_register_operand" "r") (match_operand: 4 "vpr_register_operand" "Up")] - VADDQ_M_N)) + MVE_INT_M_N_BINARY)) ] "TARGET_HAVE_MVE" - "vpst\;vaddt.i%# %q0, %q2, %3" + "vpst\;t.i%# %q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) ;; -;; [vaddq_m_u, vaddq_m_s]) +;; [vaddq_m_u, vaddq_m_s] +;; [vsubq_m_u, vsubq_m_s] +;; [vmulq_m_u, vmulq_m_s] ;; -(define_insn "mve_vaddq_m_" +(define_insn "@mve_q_m_" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") (match_operand: 4 "vpr_register_operand" "Up")] - VADDQ_M)) + MVE_INT_M_BINARY)) ] "TARGET_HAVE_MVE" - "vpst\;vaddt.i%# %q0, %q2, %q3" + "vpst\;t.i%# %q0, %q2, %q3" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5422,40 +5332,6 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vmulq_m_n_u, vmulq_m_n_s]) -;; -(define_insn "mve_vmulq_m_n_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "s_register_operand" "r") - (match_operand: 4 "vpr_register_operand" "Up")] - VMULQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vmult.i%# %q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vmulq_m_s, vmulq_m_u]) -;; -(define_insn "mve_vmulq_m_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:MVE_2 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VMULQ_M)) - ] - "TARGET_HAVE_MVE" - "vpst\;vmult.i%# %q0, %q2, %q3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vornq_m_u, vornq_m_s]) ;; @@ -5796,23 +5672,6 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vsubq_m_n_s, vsubq_m_n_u]) -;; -(define_insn "mve_vsubq_m_n_" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand: 3 "s_register_operand" "r") - (match_operand: 4 "vpr_register_operand" "Up")] - VSUBQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vsubt.i%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vhcaddq_rot270_m_s]) ;; @@ -6612,36 +6471,40 @@ (set_attr "length""8")]) ;; -;; [vaddq_m_f]) +;; [vaddq_m_f] +;; [vsubq_m_f] +;; [vmulq_m_f] ;; -(define_insn "mve_vaddq_m_f" +(define_insn "@mve_q_m_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") (match_operand: 4 "vpr_register_operand" "Up")] - VADDQ_M_F)) + MVE_FP_M_BINARY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vaddt.f%# %q0, %q2, %q3" + "vpst\;t.f%# %q0, %q2, %q3" [(set_attr "type" "mve_move") (set_attr "length""8")]) ;; -;; [vaddq_m_n_f]) +;; [vaddq_m_n_f] +;; [vsubq_m_n_f] +;; [vmulq_m_n_f] ;; -(define_insn "mve_vaddq_m_n_f" +(define_insn "@mve_q_m_n_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand: 3 "s_register_operand" "r") (match_operand: 4 "vpr_register_operand" "Up")] - VADDQ_M_N_F)) + MVE_FP_M_N_BINARY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vaddt.f%# %q0, %q2, %3" + "vpst\;t.f%# %q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -6985,40 +6848,6 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vmulq_m_f]) -;; -(define_insn "mve_vmulq_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VMULQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vmult.f%# %q0, %q2, %q3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vmulq_m_n_f]) -;; -(define_insn "mve_vmulq_m_n_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "s_register_operand" "r") - (match_operand: 4 "vpr_register_operand" "Up")] - VMULQ_M_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vmult.f%# %q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vornq_m_f]) ;; @@ -7053,40 +6882,6 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vsubq_m_f]) -;; -(define_insn "mve_vsubq_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VSUBQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vsubt.f%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vsubq_m_n_f]) -;; -(define_insn "mve_vsubq_m_n_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand: 3 "s_register_operand" "r") - (match_operand: 4 "vpr_register_operand" "Up")] - VSUBQ_M_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vsubt.f%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vstrbq_s vstrbq_u] ;; @@ -8927,34 +8722,6 @@ "vstrw.32\t%q2, [%0, %q1, uxtw #2]" [(set_attr "length" "4")]) -;; -;; [vaddq_s, vaddq_u]) -;; -(define_insn "mve_vaddq" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (plus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w"))) - ] - "TARGET_HAVE_MVE" - "vadd.i%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vaddq_f]) -;; -(define_insn "mve_vaddq_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (plus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w"))) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vadd.f%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") -]) - ;; ;; [vidupq_n_u]) ;;