From: Judith Mendez Date: Mon, 9 Feb 2026 17:23:29 +0000 (-0600) Subject: dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells support X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b0ea5175358f0872ffdc9c6073585637dc01815a;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells support Add optional nvmem-cells and nvmem-cell-names properties to support reading silicon revision information from alternate location using NVMEM providers. This is used on AM62P to read GP_SW1 register for accurate silicon revision detection. Signed-off-by: Judith Mendez Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260209172330.53623-2-jm@ti.com Signed-off-by: Nishanth Menon --- diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml index dada28b47ea07..2900224aac743 100644 --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml @@ -15,6 +15,9 @@ description: | represented by CTRLMMR_xxx_JTAGID register which contains information about SoC id and revision. + On some SoCs like AM62P, the silicon revision is determined by reading + alternative registers via NVMEM cells. + properties: $nodename: pattern: "^chipid@[0-9a-f]+$" @@ -26,6 +29,14 @@ properties: reg: maxItems: 1 + nvmem-cells: + items: + - description: Alternate silicon revision register + + nvmem-cell-names: + items: + - const: gpsw1 + required: - compatible - reg