From: Dejan Jevtic <dejan.jevtic@valgrind.org>
Date: Thu, 27 Feb 2014 14:17:19 +0000 (+0000)
Subject: mips32: Fpu guest registers are ULong and the initial values need to be
X-Git-Tag: svn/VALGRIND_3_10_1^2~143
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b24120b5a36756d23864ce08e723483a4ab5c67f;p=thirdparty%2Fvalgrind.git

mips32: Fpu guest registers are ULong and the initial values need to be
extended.

Because we are supporting both big and little endian mips32 we need to
make sure that the initial values for the fpu registers are the same for both
endian.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2827
---

diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c
index 92580165d3..51bc2e73df 100644
--- a/VEX/priv/guest_mips_helpers.c
+++ b/VEX/priv/guest_mips_helpers.c
@@ -105,38 +105,38 @@ void LibVEX_GuestMIPS32_initialise( /*OUT*/ VexGuestMIPS32State * vex_state)
    vex_state->guest_LO = 0;   /* Multiply and divide register lower result */
 
    /* FPU Registers */
-   vex_state->guest_f0 = 0x7ff80000;   /* Floting point general purpose registers */
-   vex_state->guest_f1 = 0x7ff80000;
-   vex_state->guest_f2 = 0x7ff80000;
-   vex_state->guest_f3 = 0x7ff80000;
-   vex_state->guest_f4 = 0x7ff80000;
-   vex_state->guest_f5 = 0x7ff80000;
-   vex_state->guest_f6 = 0x7ff80000;
-   vex_state->guest_f7 = 0x7ff80000;
-   vex_state->guest_f8 = 0x7ff80000;
-   vex_state->guest_f9 = 0x7ff80000;
-   vex_state->guest_f10 = 0x7ff80000;
-   vex_state->guest_f11 = 0x7ff80000;
-   vex_state->guest_f12 = 0x7ff80000;
-   vex_state->guest_f13 = 0x7ff80000;
-   vex_state->guest_f14 = 0x7ff80000;
-   vex_state->guest_f15 = 0x7ff80000;
-   vex_state->guest_f16 = 0x7ff80000;
-   vex_state->guest_f17 = 0x7ff80000;
-   vex_state->guest_f18 = 0x7ff80000;
-   vex_state->guest_f19 = 0x7ff80000;
-   vex_state->guest_f20 = 0x7ff80000;
-   vex_state->guest_f21 = 0x7ff80000;
-   vex_state->guest_f22 = 0x7ff80000;
-   vex_state->guest_f23 = 0x7ff80000;
-   vex_state->guest_f24 = 0x7ff80000;
-   vex_state->guest_f25 = 0x7ff80000;
-   vex_state->guest_f26 = 0x7ff80000;
-   vex_state->guest_f27 = 0x7ff80000;
-   vex_state->guest_f28 = 0x7ff80000;
-   vex_state->guest_f29 = 0x7ff80000;
-   vex_state->guest_f30 = 0x7ff80000;
-   vex_state->guest_f31 = 0x7ff80000;
+   vex_state->guest_f0 = 0x7ff800007ff80000;   /* Floting point GP registers */
+   vex_state->guest_f1 = 0x7ff800007ff80000;
+   vex_state->guest_f2 = 0x7ff800007ff80000;
+   vex_state->guest_f3 = 0x7ff800007ff80000;
+   vex_state->guest_f4 = 0x7ff800007ff80000;
+   vex_state->guest_f5 = 0x7ff800007ff80000;
+   vex_state->guest_f6 = 0x7ff800007ff80000;
+   vex_state->guest_f7 = 0x7ff800007ff80000;
+   vex_state->guest_f8 = 0x7ff800007ff80000;
+   vex_state->guest_f9 = 0x7ff800007ff80000;
+   vex_state->guest_f10 = 0x7ff800007ff80000;
+   vex_state->guest_f11 = 0x7ff800007ff80000;
+   vex_state->guest_f12 = 0x7ff800007ff80000;
+   vex_state->guest_f13 = 0x7ff800007ff80000;
+   vex_state->guest_f14 = 0x7ff800007ff80000;
+   vex_state->guest_f15 = 0x7ff800007ff80000;
+   vex_state->guest_f16 = 0x7ff800007ff80000;
+   vex_state->guest_f17 = 0x7ff800007ff80000;
+   vex_state->guest_f18 = 0x7ff800007ff80000;
+   vex_state->guest_f19 = 0x7ff800007ff80000;
+   vex_state->guest_f20 = 0x7ff800007ff80000;
+   vex_state->guest_f21 = 0x7ff800007ff80000;
+   vex_state->guest_f22 = 0x7ff800007ff80000;
+   vex_state->guest_f23 = 0x7ff800007ff80000;
+   vex_state->guest_f24 = 0x7ff800007ff80000;
+   vex_state->guest_f25 = 0x7ff800007ff80000;
+   vex_state->guest_f26 = 0x7ff800007ff80000;
+   vex_state->guest_f27 = 0x7ff800007ff80000;
+   vex_state->guest_f28 = 0x7ff800007ff80000;
+   vex_state->guest_f29 = 0x7ff800007ff80000;
+   vex_state->guest_f30 = 0x7ff800007ff80000;
+   vex_state->guest_f31 = 0x7ff800007ff80000;
 
    vex_state->guest_FIR = 0;  /* FP implementation and revision register */
    vex_state->guest_FCCR = 0; /* FP condition codes register */