From: Lijo Lazar Date: Thu, 27 Nov 2025 10:41:46 +0000 (+0530) Subject: drm/amd/pm: Use common helper for smuv13.0.7 dpm X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b2debbbb60f19ecec9567a518ef02ea40cdf89a4;p=thirdparty%2Fkernel%2Flinux.git drm/amd/pm: Use common helper for smuv13.0.7 dpm Use helper function to print smuv13.0.7 dpm tables to sysfs. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index ff9ad5bdf138..1465e0c80175 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -1174,9 +1174,8 @@ static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu, OverDriveTableExternal_t *od_table = (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; int i, curr_freq, size = *offset, start_offset = *offset; - struct smu_dpm_table *single_dpm_table; + struct smu_dpm_table *single_dpm_table = NULL; struct smu_pcie_table *pcie_table; - uint32_t pcie_speed, pcie_width; uint32_t gen_speed, lane_width; int32_t min_value, max_value; int ret = 0; @@ -1210,61 +1209,6 @@ static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu, case SMU_DCEFCLK: single_dpm_table = &(dpm_context->dpm_tables.dcef_table); break; - default: - break; - } - - switch (clk_type) { - case SMU_SCLK: - case SMU_MCLK: - case SMU_SOCCLK: - case SMU_FCLK: - case SMU_VCLK: - case SMU_VCLK1: - case SMU_DCLK: - case SMU_DCLK1: - case SMU_DCEFCLK: - ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); - if (ret) { - dev_err(smu->adev->dev, "Failed to get current clock freq!"); - return ret; - } - - if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) { - /* - * For fine grained dpms, there are only two dpm levels: - * - level 0 -> min clock freq - * - level 1 -> max clock freq - * And the current clock frequency can be any value between them. - * So, if the current clock frequency is not at level 0 or level 1, - * we will fake it as three dpm levels: - * - level 0 -> min clock freq - * - level 1 -> current actual clock freq - * - level 2 -> max clock freq - */ - if ((single_dpm_table->dpm_levels[0].value != curr_freq) && - (single_dpm_table->dpm_levels[1].value != curr_freq)) { - size += sysfs_emit_at(buf, size, "0: %uMhz\n", - single_dpm_table->dpm_levels[0].value); - size += sysfs_emit_at(buf, size, "1: %uMhz *\n", - curr_freq); - size += sysfs_emit_at(buf, size, "2: %uMhz\n", - single_dpm_table->dpm_levels[1].value); - } else { - size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", - single_dpm_table->dpm_levels[0].value, - single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); - size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", - single_dpm_table->dpm_levels[1].value, - single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); - } - } else { - for (i = 0; i < single_dpm_table->count; i++) - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", - i, single_dpm_table->dpm_levels[i].value, - single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); - } - break; case SMU_PCIE: ret = smu_v13_0_7_get_smu_metrics_data(smu, METRICS_PCIE_RATE, @@ -1279,32 +1223,8 @@ static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu, return ret; pcie_table = &(dpm_context->dpm_tables.pcie_table); - for (i = 0; i < pcie_table->lclk_levels; i++) { - pcie_speed = DECODE_GEN_SPEED(pcie_table->pcie_gen[i]); - pcie_width = - DECODE_LANE_WIDTH(pcie_table->pcie_lane[i]); - size += sysfs_emit_at( - buf, size, "%d: %s %s %dMhz %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : - (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : - (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : - (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : - "", - (pcie_table->pcie_lane[i] == 1) ? "x1" : - (pcie_table->pcie_lane[i] == 2) ? "x2" : - (pcie_table->pcie_lane[i] == 3) ? "x4" : - (pcie_table->pcie_lane[i] == 4) ? "x8" : - (pcie_table->pcie_lane[i] == 5) ? "x12" : - (pcie_table->pcie_lane[i] == 6) ? "x16" : - "", - pcie_table->lclk_freq[i], - (gen_speed == pcie_speed && - lane_width == pcie_width) ? - "*" : - ""); - } - break; - + return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed, + lane_width, buf, offset); case SMU_OD_SCLK: if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) @@ -1522,6 +1442,18 @@ static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu, break; } + if (single_dpm_table) { + ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, + &curr_freq); + if (ret) { + dev_err(smu->adev->dev, + "Failed to get current clock freq!"); + return ret; + } + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + curr_freq, buf, offset); + } + *offset += size - start_offset; return 0;