From: CL Wang Date: Mon, 15 Dec 2025 13:23:47 +0000 (+0800) Subject: spi: dt-bindings: Add support for ATCSPI200 SPI controller X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b2f06783081859b200a853f9682d831b6fc9982d;p=thirdparty%2Fkernel%2Flinux.git spi: dt-bindings: Add support for ATCSPI200 SPI controller Document devicetree bindings for the Andes ATCSPI200 SPI controller. Signed-off-by: CL Wang Acked-by: Conor Dooley Link: https://patch.msgid.link/20251215132349.513843-2-cl634@andestech.com Signed-off-by: Mark Brown --- diff --git a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml new file mode 100644 index 0000000000000..78093468dd5e9 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/andestech,ae350-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes ATCSPI200 SPI controller + +maintainers: + - CL Wang + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-spi + - const: andestech,ae350-spi + - const: andestech,ae350-spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + num-cs: + description: Number of chip selects supported + maxItems: 1 + + dmas: + items: + - description: Transmit FIFO DMA channel + - description: Receive FIFO DMA channel + + dma-names: + items: + - const: tx + - const: rx + +patternProperties: + "@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + spi-rx-bus-width: + enum: [1, 4] + + spi-tx-bus-width: + enum: [1, 4] + +allOf: + - $ref: spi-controller.yaml# + +required: + - compatible + - reg + - clocks + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + spi@f0b00000 { + compatible = "andestech,ae350-spi"; + reg = <0xf0b00000 0x100>; + clocks = <&clk_spi>; + dmas = <&dma0 0>, <&dma0 1>; + dma-names = "tx", "rx"; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + }; + };